Table of Contents
Advertisement
ADVANCED TECHNIQUES
5.6kQ
+ 5 V - - - - - . . . - - - . - - - ' V I . / v - - - - - ,
DATA
+2V VREF
74164
2920
SHIFT
REGISTER
M1
SIG OUT 0
+ 5 V -
CLOCK
~-------------~~
Figure
6-5.
Logic Diagram for Digital Output: Serial
With a 10 MHz clock a transfer rate of 55 K Bytes per
second is obtained for each instruction sequence or as
high as 220 K Bytes/second per program pass.
Note that the clocking by CCLK requires that the
overflowing instruction be located as shown in
the diagram. The CCLK signal will occur during in-
structions
which
are
a
multiple
of
four.
The
conditional test on the data and the potential overflow
must
be
done
with
two
separate
instruc-
tions. A conditional overflow instruction will assert OF
even
if
the
condition
is
not
met.
(Figure
6-6)
Overflows may occur during other portions of the pro-
gram since there will be no clocking of the shift register.
OVERFLOW DURING
INSTRUCTION 2
Input Parallel-For synchronous parallel input of one
byte per program pass with the 2920 as master. Table
6-5 shows the instruction sequence.
With a 10 MHz clock a transfer rate of 37.5 K Byte/sec
is obtained for each instruction sequence which is once
per program pass if the EOP is used for the control
signal.
This method uses all analog input pins, often an unac-
ceptable'demand. Using fewer pins slows the data rate
only slightly since the majority of the time is spent in
sampling and converting rather than data manipulation.
(See Figure 6-7.) Table 6-5 shows the instruction
sequence.
INSTRUCTION
TIME~
Figure
6-6.
Timing Diagram
6-7
Advertisement
Table of Contents
