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ADVANCED TECHNIQUES
instructions put the input bit in the DAR. The max-
imum input rate is determined by the size of the input
sample and hold capacitor. The threshold between a
zero and a one can be set anywhere between 0 and
±
VREF by what is initially in the DAR.
SIGOUT (K). These eight outputs can provide a logical
one and zero at any two voltage levels between
±
VREF
with a load DAR and OUT (K) sequence. Open drain
TTL levels are possible in groups of four output pins
controlled by MI and M2 if
VREF~
1.5 volts. External
pull-up resistors should be used. Speed is the same for
either analog or TTL output mode.
OF. This open drain output provides a high speed TTL
output which may be set or cleared with a single
instruction.
CCLK. This open drain clock signal which occurs every
four instruction executions, although always present,
provides a convenient activating signal for digital I/O
transfers.
RST /EOP. As an open drain output the EOP is a con-
venient clock or control signal for transfers which
occurs only once per program pass. RST can be a non-
synchronous control input when gated with CCLK.
Each complete 110 operation may consist of four dif-
ferent operations; a control sequence, a data assembly
or put-away sequence, a data transfer sequence and a
clocking or activation sequence. Specific examples are
given using the different inputs and outputs on the 2920.
The examples are not exhaustive but they show some
representative sequences for the four functions in a
complete 110 operation.
Output Parallel-For synchronous parallel output of
one byte (8 bits) per program pass with the 2920 as
master (see Figure 6-4). Table 6-3 shows the instruction
sequence.
Table 6-3. Digital Output: Parallel
Instruction Sequence.
LDA
LDA
LDA
LDA
LDA
LDA
OUT7
LDA
OUTO
Summary:
DAR,
DATA
D7,
KPO
DO,
KPO
D7,
KP7,
DO,
KP7,
DAR,
D7
DAR,
DO
Analog instructions
Digital instructions
Input pins
Output pins
Data memory locations
Overflow
CND7
CNDO
8 +8B*
17
o
8
8
Load output byte into DAR
Initialize Data buffers
DO-D7 to zero.
Load +FS to data buffers
if tested bit
=
I
Output Data buffers
DO-D7 on Outputs 0-7
Not affected
*B equals the number of analog NOP and OUT instructions needed for the device and clock rate
used. See Chapter 3 for analog design rules.
6-5
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