Intel 2920 Design Handbook page 29

TH E 2920 SIGNAL PROCESSOR
PIN DESCRIPTIONS (RUN MODE)
Symbol Function
SIGOUT
8 PinS corresponding to the 8 demultl-
plexed analog outputs (0-7)
GROA Analog signal ground held at or near
GROO tYPically
CAP, & CAP2 External capacitor connections for the
Input signal sample and hold CirCUit
VREF Input Reference Voltage
SIGIN
4 pins corresponding to the 4 multi-
plexed analog Inputs (0-3)
VBB
Most negative power Pin set at -5 volts
dUring run mode (different voltage In
program mode)
X1/CLK Clock Input when uSing external clock
signals, OSCillator Input for external
crystal when uSing Internal clock
X2
OSCillator Input for external crystal when
uSing Internal clock
GROO Digital ground
Vee 5 volts In run mode
CCLK
Internal fetch cycle clock output The
failing edge designates the START of a
new PROM fetch cycle. CCLK IS 1/16 of
X1/CLK rate.
RUN/PROG Mode control tied to GROO In run mode
(different voltage In program mode)
RST/EOP Low RST input initializes program fetch
counter to first location. As an output It
Signifies EOP instruction present (open
drain, active low).
PIN DESCRIPTIONS (PROGRAM MODE)
Symbol
00,01,02,03
Function
4 pins carrying EPROM program data for
both input and output (open drain, active
low output; active high Input)
VB" VB2 VB3 Digital ground In PROGRAM mode (dif-
ferent voltage for RUN mode)
VS" VS2, VS3 +5 volts In PROGRAM mode (function
changes for RUN mode)
RUN/PROG Mode control pin tied to VBB for
PROGRAM mode (voltage changes for
RUN mode)
INCR Input pulse Increments the nibble
(4-blts) counter In PROG mode (func-
tion changes In RUN mode)
VSP
PROGIVER
EPROM po\',er pin +5 volts for VERIFY
mode and +25 volts for PROGRAM
mode (different voltage In RUN mode)
Controls EPROM bl-dlrectlonal data bus
for venfy (low) or program (high)
Input pulse resets nibble counter to
POSition zero for start of programming
Symbol
OF
VSP
M1, M2
Function
Indicates an overflow In the current ALU
operation (open drain, active low)
EPROM power Pin 0 volts for RUN mode
(Different voltage In program mode)
Two pins which specify the output mode
of the SIGOUT pins (see Table 4)
SIGOUT 3 SIGOUT 2
SIGOUT 4 SIGOUT 1
SIGOUT 5 SIGOUT 0
GROA M1
SIGOUT 6 M2
SIGOUT 7 VSP
CAP,
OF
VREF RST/EOP
CAP 2
RUN/PROG
SIGIN 0 CClK
SIGIN 3 Vee
V BB
GROO
SIGIN 2
X 2
SIGIN 1
XI/ClK
Run Mode Pin Configuration.
03
02
01
00
VSl
PROG/VER
VSP
INCR
RST
RUN/PROG
Program Mode Pin Configuration.
Figure 3-2. 2920 Pin Descriptions
3-4