Intel 2920 Design Handbook page 131

Analog signal processor
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2920 FUNCTIONAL BLOCKS NEEDED
BPF:
4 Complex Pole Pairs
1 Complex Zero Pair
2 Real Zeros
LPF:
2 Complex Pole Pairs
1 Real Pole
1 Complex Zero Pair
AlC:
Simple Pole Filter and Divide Algorithm
DELAY:
2 Register Delay Line: Delay will be 1471's II Sample
Rate is 13.6 kHz
MULTIPLY: 9 Bit x 25 Bit (9 Bits are Adequate Because of 9 Bit
AID Conversion)
2 Threshold Detectors
Voltage Controlled Sine Wave Oscillator
1 9 Bit Input
2 Digital Inputs (1 Bit)
2 Outputs
WORKSHEET #1
2920 BUILDING BLOCK SUMMARY
"Of
" 01
Total
"
Tolal
APPENDIX
Function
Comments
Inst's
Inst's RAM
RAM DAR
4 Qu.drant Multiply
20uadran! Multiply
ConstanlMulliply
4 Quadrant DIVide
Complex Pole Pair
16 Bit )(25 Bit
9 BII )(25 Bit
12
18
26
10
Complex Zero Pa.,
When hnked with pole/separate
2
5 10(7 1
Full Quadrant S.cllon
Pole
+
Zero
Pllr
1222
34
Singl. Real Pol.
26
12
\lngl. Real Zero
When hnked with pole/separate
2
2 Cascaded Qu.dradlcs
2 Pole
+
Zero Pairs
J Pole, 2 Zero Filler
1 Real and 1 Complex Pole
Sawtooth Wave Generator
37
Tnangle Wave Generalor
SlneW,vaGenerator
SLO Sweeping
'1CO (voltage controlled
oscillator)
Full Wave Rectifier
Trapezoidal Waveform (5% THD)
Sine Wave
FWR
+
Single Pole LPF
Envelope detector
Threshold Detector
Ale
DIVide +LPF
Unit Delay
1
Sample Period
Subtotal
Overhead
TOTAL
1120
8%
14
27
152
A-8
To calculate the number of RAM locations for a filter which
contains poles and zeros, use the formula for the cascaded
quadradic sections,
#
RAM
=
n
+
2, where n
=
#
of poles (corre-
sponding to the number of delay elements needed).

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