Intel 2920 Design Handbook page 34

THE 2920 SIGNAL PROCESSOR
SIGINO
SIGINl
SIGIN2
SIGIN3
FROM PROM
110
CAPl CAP2 AGND
CND TEST BIT
SIGOUTO
SIGOUT1
SIGOUT2
SIGOUT3
SIGOUT4
SIGOUT5
SIGOUT6
SIGOUT7
VREF
Figure 3-5. Analog Section Block Diagram
All operations of this section are controlled by a five-bit
control field. It can be divided into two subfields: a two-
bit function selector and a three-bit modifier field.
Table 3-6 summarizes the analog section operations.
Giving the most significant bits first, the function select
bits are designated ADF1 and ADFO; the modifier bits
are ADK2, ADK1, and ADKO.
The basis analog functions are as follows:
Execution of one or more "IN" instructions provides
a sample of one of the input leads. Several such
instructions may need to be executed in sequence due
to the time constants of the sample capacitor charg-
ing circuit.
The sample is converted to its digital equivalent by a
series of "CVT" instructions in descending order.
The digital equivalent is produced in the DAR, which
may then be read by the arithmetic section.
Calculated results in the DAR may be delivered to an
output pin via "OUT" instructions. Several such
instructions may need to be executed in sequence due
to the time constants of the output sample capacitor
charging circuit.
Input and output sample rates are determined by the
frequency of execution of input/conversion sequences
and output instructions, respectively.
3-9
The input channel multiplexer consists of four analog
switches which directly connect a common external
sampling capacitor to the input terminals. The size of
the sample capacitor affects the time constant of the
sampling circuit and offset due to charge coupled
through the sampling switches. The recommended
values for the sample capacitor are between 100 pf and
1000 pf depending on clock rate. Acquisition time for a
100 pf sample capacitor is less than 2400 nsec. Thus, for
this value of sample capacitor, a sequence of six "IN"
instructions should be used to sample each input, when
operating at 10 MHz.
The sample and hold capacitor may be selected based on
two "cookbook" formulae:
S to H offset
=
VINPUT (PEAK to PEAK)/Capacitance
(in pf)
Acquisition Time (Seconds)
=
2400 x Capacitance (in
Farads)
Note that the sample capacitor is shared among all
inputs. Its selection must be based on the most stringent
combination of input parameters.
The analog to digital conversion system uses successive
approximation via a binary search routine under pro-
gram control. Using the CVTS and CVT(K) instructions
in descending sequence allows up to a 9-bit digital
representation of an input sample into the DAR.