Intel 2920 Design Handbook page 81

ADVANCED TECHNIQUES
Table 6-5.
Digital Input: Parallel
Instruction Sequence.
LOA DAR, KP7
OUT
0
LOA
DAR,
KP2
IN3
CVT3
INO
CVTO
SUB
DAR,
KP2
LOA 0, DAR,
DOA, 0,
LOA DAR, KPO
aUTO
LOA DAR,
KP2
IN3
CVT3
INO
CVTO
SUB DAR, KP2
XOR 0, DAR
Summary:
Analog instructions
Digital instructions
Input pins
Output pins
Data memory locations
Overflow
L2
L2
Select higher order four bits
Load DAR
+
FS/4
Input Bit 3
Convert Bit 3
Repeat through Bit 0
DAR contains four higher order bits
MSB's
Left shift DAR four bits and store in 0
Select lower order
four bits.
Load DAR FS/4
DAR contains four lower order bits
Combine high and low order bits
SA
+
2B
+
8C*
9
4
I
I
Not affected
*
A equals the number of IN instructions and C equals the CVT and NOP instruction needed for
the device and clock rate used. See Chapter 3 for analog design rules.
6-8