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ADVANCED TECHNIQUES
07
DATA
IN
DO
DATA TAKEN
SELECT I
4Y
•
·
·
.
·
74157
.
· · ·
1Y
•
ISTROBE
...L
+5V
1.5k
15k
~'"
l
56kQ
SIGIN 3
. .
SIGIN 0
2kQ
1
I
IEOP
2920
SiG'OliTo
VREF
-
~
56K
+2V
+5V
Figure 6-7. Logic Diagram for Digital Input: Parallel
Input
Parallel-Serial- This example reduces the
number
of analog
inputs
committed
to
digital
parameters yet accepts parallel loads. The transfer is
synchronous with the 2920 as master and multiple bytes
can transfer per program pass (see Figure 6-8). Table 6-6
shows the instruction sequence.
T
LOAD}
1
CLOCK INHIBIT
DATATAKEN
LOAD DATA
SERIAL 1.5kQ
07
-
.
OUT
:
74165
:
DATA IN
DO
-
ICLOCK
With a 10 MHz clock a transfer rate of 30K Bytes/sec is
obtained for the instruction sequence or up to twice that
amount per full program pass.
+5V
SIGIN 0
2.kQ
-=
5.6kQ
~O
2920
SIGOUT 1
•
VREF
M1
lOF
+2V
+5V
Figure 6-8. Logic Diagram for Digital Input: Parallel-Serial
6-9
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