Intel 2920 Design Handbook page 31

THE 2920 SIGNAL PROCESSOR
The DAR can be used as a source or a destination
operand. It is both a digital to analog register and an
analog to digital register. It is nine bits wide, occupying
the nine most significant bit positions of a word whose
other bits are set to ones in order to correct for
AID
conversion number system offset when read into the
processor.
The DAR output is also tied directly to the digital to
analog converter (DI A) inputs. The DAR is used as a
successive-approximation register for analog to digital
conversion, under control of the analog function
instruction field. Each bit position of the DAR can also
be tested by the ALU for conditional arithmetic
operations.
Table 3-3. Scaler Codes and Operations
Scaler Bit
Equivalent
Code Values
Multiplier Operation
L02 1110
22= 4.0 "A"x22
LOI
1101 2'= 2.0
"A"x21
ROO 1111
2°= 1.0 "A"x2°
ROI 0000
2- 1 =0.5 "A"x2- 1
R02 0001
2- 2 = 0.25
R03
0010
2- 3 = 0.125
R04
0011
2-
4
= 0.0625 "A"x2-
4
R05 0100
2-
5
= 0.03125
Scaler-The scaler is an arithmetic barrel shifter
located between the A port of the RAM and the ALU.
Values read from the A port can be shifted left or right.
The shifts can be a maximum of two positions to the left
or a maximum of thirteen positions right. Left shifts fill
with zeroes at the right; right shifts fill with the sign bit
at the left.
As explained above, these arithmetic shifts are
equivalent to multiplication of the A port value by a
power of two, where the number of positions shifted is
the 2' s power.
The scaler is controlled by a 4-bit wide control field
from the EPROM, as shown in Table 3-3. Note that left
shifts may produce numbers which are too large to fit
within a 25-bit field. The handling of such large
numbers is described in the ALU section below.
The
ALU-
The Arithmetic Logic Unit calculates a
25-bit result from its A and B operands (source and
destination) based on an operation code from the
EPROM. The 25-bit result is written back into the B
(destination) memory location at the end of the
instruction cycle.
One condition for overflow is a left shift where the sense
of the sign bit changes. For this reason the ALU uses
extended precision to allow calculation of the correct
3-6
Scaler Bit
Equivalent
Code Values Multiplier
R06
0101
2
6
= 0.015625
R07
0110 2
7
= 0.0078125
R08 0111
2
8
= 0.00390625
R09 1000
2-
9
= 0.001953125
RIO 1001
2- 1 °= 0.0009765625
Rll 1010
2- 11 = 0.00048828125
R12 1011
2 12 =0.000244140625
R13
1100
2 -13=0.0001220703125
result even when receiving left-shifted operands from
the scaler. If the computed result YY exceeds the
bounds
-l.O~YY<l.O
an overflow condition is indicated. When overflow
limiting is enabled, this condition causes the result to be
replaced with the legal value closest to the desired result,
i.e., with -1 if the computed value was negative, and
with
+
1.0 if the result was positive.
In binary these extreme values appear as
Binary Value
1000 000 000 000 000 000 000 000 -1.0
0111 111
111
111
111
111
111 111
1-2-
24
respectively. This overflow saturation characteristic is
useful for realizing certain non-linear functions such as
limiters, and is beneficial to the stability of filters. The
OF pin indicates that an overflow is occurred on the
previous operation (cycle). This output is active low and
open-drain. In the case where overflow is not enabled,
each binary number is extended to 28-bit precision by
extending the sign bit to the left. The calculation is done
a!1d the low 25 bits are written back to the destination.