Intel 2920 Design Handbook page 130

APPENDIX
BLOCK DIAGRAM BROKEN DOWN
INTO 2920 FUNCTION BLOCKS
RECEIVER
i------------l
"FREC DETECTOR"
TRANSMITIER
DIGITAL
~ OLTAGECONTROLLED
IN
ci'~~~L~~~ER
~~------~
~
FSK.
~
J
BPF:
F(s)
LPF:
FUNCTIONAL BLOCK DETAILS
(Supplied by Customer)
G S2+AoS+Bo
(5)
=
(S+A1)(S4A2S+B2l(S2+A3S+B3)
DELAY:
147,,5 (90'C Phase Shift at 1700Hz,the Modem Center Frequency)
THRESHOLD DETECTOR:
2 Detectors to Dlscrlmlnato the 900 Hz, 1200 Hz and 2200 Hz Tones
A-7
The purpose of the limiter is to generate a square wave
representation of the input signal which will contain the fre-
quency information and provide a constant amplitude regard-
less of input signal level. This limiting is a nonlinear process
and generates harmonics which will be reflected around the
sampling frequency in a sampled data system. 80, in the 2920,
the signal level normalization is accomplished with an auto-
matic level control, which will not add additional harmonic
content to the signal.
Typically, filters will be specified as transfer functions in
the 8 domain. The number of zeros can be determined from the
numerator terms, and the number of poles from the denomina-
tor terms. Quadradic terms will, in general, represent a
complex pole (zero) pair.