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SAM PLED DATA SYSTEMS
The signal-to-noise ratio (SNR) of a sampled sinusoid
sin(wT) due to jitter uniformly distributed over
-T~TO~T
seconds is
Mean Square Signal
Mean Square Noise
= (SNR)
jitter
3
(WT)
2
2
Expressed another way,
(SNR)
..
=
0.038
(~)2
JItter
T
where T is the period of the sampled signal. The jitter
SNR is plotted in Figure 2-8 as a function of the jitter-
tolerance ratio T/T.
rg
-'UI
<tUl
z-
,,0
iii
Z
WUl
a: a::
<t<
::J:l
0°
cn
Ul
ZZ
<t<
wUl
::;:i:
a:
z
III
I
r
LOG SCALE
IlJ..U..l.LL..J
"-
10
5
2
1
100
~
~
80
60
40
20
o
10-6
~
~
""
~
10-
5
10- 3
JITTER TOLERANCE,
T
MINIMUM SIGNAL PERIOD, T
Figure 2-8. Jitter SNR
""
Since each pass of the 2920 program uses the same
number of clock cycles, overall sampling jitter will be
entirely a function of the clock stability. When the 2920
clock is crystal controlled, clock/sampling jitter will be
insignificant.
2-6
2.2.4 Quantization Noise
Digital signal processing of a signal implies that at
specific times the signal is sampled and a digital word is
formed that represents the amplitude of the signal at
that time. The sections above described the effect of this
sampling process, and showed that a minimum loss of
information is possible with the proper selection of the
input filter and sampling frequency.
The conversion from a continuous signal to a digital
signal requires that signal voltage be divided into a finite
number of levels which can be defined using a digital
word n bits long. An n-bit word can describe 2 n dif-
ferent voltage steps. Signal variations between these
steps will go undetected. It is therefore necessary to
determine the range of signal levels from maximum to
minimum that the system must operate with, to deter-
mine the number of bits needed in an A/D conversion.
Figure 2-9 illustrates how the error voltage (called quan-
tization noise) is generated. The corresponding ratio of
peak signal to quantization noise, expressed in dB, is a
function of the digital word length.
OUTPUT
VOLTAGE
Ja
=
2N-1
N
=
It BITS
Ja '
6N OB
I
MAX
I
ERROR
I
1
:
VOLTAGE"
"
t\ "
1\
t\
I
'J 'J \I \I \I ' \
INPUT
VOLTAGE
INPUT
VOLTAGE
2
3
4
5
6
7
8
91011
SINO
DB
"6 18
24
30
36
42
48
54
60
66
Figure 2-9. Quantization Noise
The quantizing error can be expressed in terms of the
total mean squared error voltage between the exact and
the quantized samples of the signal. In Figure 2-10, any
signal voltage v(t) falls between the i-th and the (i+ 1 )th
levels which define the i-th quantizing interval. The
error signal ei is expressed as
ei=V(t)-Vi
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