Analog Devices ADSP-2181 Manual page 20

ADSP-2181/ADSP-2183
ADSP-2181
Parameter
Clock Signals and Reset
Timing Requirements:
t CLKIN Period
CKI
t
CLKIN Width Low
CKIL
t CLKIN Width High
CKIH
Switching Characteristics:
t CLKOUT Width Low
CKL
t CLKOUT Width High
CKH
t CLKIN High to CLKOUT High
CKOH
Control Signals
Timing Requirements:
t RESET Width Low
RSP
ADSP-2183
Parameter
Clock Signals and Reset
Timing Requirements:
t CLKIN Period
CKI
t CLKIN Width Low
CKIL
t CLKIN Width High
CKIH
Switching Characteristics:
t CLKOUT Width Low
CKL
t CLKOUT Width High
CKH
t CLKIN High to CLKOUT High
CKOH
Control Signals
Timing Requirements:
t RESET Width Low
RSP
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
Min
60
20
20
0.5t – 7
CK
0.5t – 7
CK
0
1
5t
CK
Min
69.4
20
20
0.5t – 7
CK
0.5t – 7
CK
0
1
5t
CK
t
CKI
t
CKIL
t
CKOH
t
CKH
t
CKL
Figure 22. Clock Signals
–20–
Max
150
20
28.8 MHz
Max
150
20
t
CKIH
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
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