Analog Devices ADSP-2181 Manual page 22

ADSP-2181/ADSP-2183
ADSP-2181/ADSP-2183
Parameter
Bus Request/Grant
Timing Requirements:
t BR Hold after CLKOUT High
BH
t BR Setup before CLKOUT Low
BS
Switching Characteristics:
t CLKOUT High to xMS,
SD
RD, WR Disable
t xMS, RD, WR
SDB
Disable to BG Low
t BG High to xMS,
SE
RD, WR Enable
t xMS, RD, WR
SEC
Enable to CLKOUT High
t xMS, RD, WR
SDBH
Disable to BGH Low
t BGH High to xMS,
SEH
RD, WR Enable
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
1
1
2
2
t
BH
CLKOUT
BR
t
BS
CLKOUT
PMS, DMS
BMS, RD
t
WR
SD
BG
t
SDB
BGH
t
SDBH
Figure 24. Bus Request–Bus Grant
Min
0.25t + 2
CK
0.25t + 17
CK
0
0
0.25t – 7
CK
0
0
t
t
SE
–22–
Max
0.25t + 10
CK
SEC
t
SEH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0