Environmental Conditions; Power Dissipation - Analog Devices ADSP-2181 Manual

ADSP-2181/ADSP-2183
ADSP-2181

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:
T = T – (PD
AMB CASE CA
T = Case Temperature in C
CASE
PD = Power Dissipation in W
= Thermal Resistance (Case-to-Ambient)
CA
= Thermal Resistance (Junction-to-Ambient)
JA
= Thermal Resistance (Junction-to-Case)
JC
Package
JA
TQFP 50 C/W
PQFP 41 C/W
1000
100
10
0
–5 25
TEMPERATURE – C
NOTES:
1. REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
Figure 8. Power-Down Supply Current (Typical)

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
Each address and data pin has a 10 pF total load at the pin.
•
The application operates at V
Total Power Dissipation = P
P = internal power dissipation from Power vs. Frequency
INT
graph (Figure 9).
)
JC CA
2 C/W 48 C/W
10 C/W 31 C/W
V = 5.5V
DD
V = 5.0V
DD
V = 4.5V
DD
55 85
2
V f
DD
= 5.0 V and t = 30 ns.
DD CK
2
+ (C V f )
INT DD
2
(C V f ) is calculated for each output:
DD
# of
Pins
Address, DMS 8
Data Output, WR 9
RD 1
CLKOUT 1
Total power dissipation for this example is P
2181 POWER, INTERNAL
570
550
530
510
490mW
480
450
420
390
365mW
360
330
300
275mW
270
240
28 29
95
90
85
80
75
75mW
70
65
60
60mW
55
50
45
47mW
40
28 29
POWER, IDLE n MODES
75
70
65
60
60mW
55
50
45
40
35
31mW
30
29mW
25
28 29
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V
3
TYPICAL POWER DISSIPATION AT 5.0V V
INSTRUCTION (CLOCK FREQUENCY REDUCTION).
4
I MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
DD
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
Figure 9. Power vs. Frequency
–14–
2
C V f
DD
2
10 pF 5 V 33.3 MHz = 66.6 mW
2
10 pF 5 V 16.67 MHz = 37.5 mW
2
10 pF 5 V 16.67 MHz =
2
10 pF 5 V 33.3 MHz =
+ 116.6 mW.
INT
V = 5.5V
DD
550mW
V = 5.0V
DD
425mW
V = 4.5V
DD
330mW
30 31 32 33 34
1/t – MHz
CK
1, 2
POWER, IDLE
V = 5.5V
DD
90mW
V = 5.0V
DD
70mW
V = 4.5V
DD
54mW
30 31 32 33 34
1/f – MHz
CK
3
IDLE;
70mW
35mW
IDLE (16)
IDLE (128)
33mW
30 31 32 33 34
1/f – MHz
CK
OR GND.
DD
DURING EXECUTION OF IDLE n
DD
4.2 mW
8.3 mW
116.6 mW
REV. 0