Related Manuals for Intel Xeon 5600 Series
Summary of Contents for Intel Xeon 5600 Series
- Page 1 Intel® Xeon® Processor 5600 Series Specification Update March 2010 Reference Number:323372-001...
- Page 2 APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
-
Page 3: Table Of Contents
Revision History ....................... 5 Preface ..........................6 Identification Information ....................8 Summary Table of Changes ..................11 Errata Summary......................14 Specification Changes....................44 Specification Clarifications ................... 45 Documentation Changes ....................46 § § Intel® Xeon® Processor 5600 Series Specification Update, March 2010... - Page 4 Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
-
Page 5: Revision History
Revision History Doc ID Revision Description Date 323372 -001 • Initial Release March 2010 Intel® Xeon® Processor 5600 Series Specification Update, March 2010... -
Page 6: Preface
This document may also contain information that was not previously published. Affected Documents Document Title Notes Intel® Xeon® Processor 5600 Series Datasheet Volume 1 & 2 323369 & 323370 Related Documents Document Title Location... -
Page 7: Identification Information
Specification changes, specification clarifications, and documentation changes are removed from the sightings report and/or specification update when the appropriate changes are made to the appropriate product specification or user documentation. Intel® Xeon® Processor 5600 Series Specification Update, March 2010... -
Page 8: Identification Information
Identification Information Component Identification The Intel® Xeon® Processor 5600 Series stepping can be identified by the following register contents. Table 1. Intel® Xeon® Processor 5600 Series Signature/Version Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number... - Page 9 Component Marking The Intel® Xeon® Processor 5600 Series can be identified by the following component markings: Figure 1. Processor Top-side Markings (Example) Table 2. Intel® Xeon® Processor 5600 Series Identification (Sheet 1 of 2) Core Frequency (GHz) Available Intel QuickPath...
- Page 10 Table 2. Intel® Xeon® Processor 5600 Series Identification (Sheet 2 of 2) Core Frequency (GHz) Available Intel QuickPath Cache S-Spec Steppin bins of Intel CPUID Interconnect (GT/s) / Size Notes Number Turbo Boost DDR3 (MHz) / DDR3L (MB) Technology (MHz) SLBWZ 0x000206C2 2.40 / 5.86 / 1333 / 1333 1/1/2/2/3/3...
-
Page 11: Summary Table Of Changes
The table included in this section indicate the errata, Specification Changes, Specification Clarifications, or Document Changes which apply to the Intel® Xeon® Processor 5600 Series. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 12 Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package Intel® Celeron® M processor Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel® processor A100 and A110 with 512-KB L2 cache Intel® Pentium® M processor Mobile Intel®...
- Page 13 AAH = Intel® Atom™ processor 300 series AAI = Intel® Xeon® processor 7400 series AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor AAK= Intel® Xeon® processor 5500 series AAL = Intel® Pentium Dual-Core processor E5000 series Intel®...
-
Page 14: Errata Summary
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ BD23 No Fix POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception BD24 No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1 Intel® Xeon® Processor 5600 Series Specification Update, March 2010... -
Page 15: Intel® Xeon® Processor 5600 Series Specification Update, March
Errata Summary Table (Sheet 2 of 4) Steppings Errata Status ERRATA Number Intel® QuickPath Memory Controller May Hang Due to Uncorrectable ECC Errors BD25 No Fix Occurring on Both Channels in Mirror Channel Mode Simultaneous Correctable ECC Errors on Different Memory Channels With Patrol BD26... - Page 16 PDPTE Uncacheable Access to a Monitored Address Range May Prevent Future Triggering BD65 No Fix of the Monitor Hardware Intel® Interconnect BIST (Intel® IBIST) Results May be Additionally Reported After BD66 No Fix a GETSEC[WAKEUP] or INIT-SIPI Sequence BD67 No Fix...
- Page 17 APIC Timer CCR May Report 0 in Periodic Mode LBR, BTM or BTS Records May have Incorrect Branch From Information After an BD80 No Fix Intel Enhanced SpeedStep Technology Transition, T-states, C1E, or Adaptive Thermal Throttling BD81 No Fix PEBS Records Not Created For FP-Assists Events MSR_TURBO_RATIO_LIMIT MSR May Return Intel®...
- Page 18 Under certain conditions as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this...
- Page 19 In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing. If the exception Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 20 Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to "Procedure Calls For Block-Structured Languages" in Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 21 Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
- Page 22 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
- Page 23 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software.
- Page 24 Workaround: As recommended in the Intel® 64 and IA-32 Intel® Architectures Software Developer’s Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception.
- Page 25 If an uncorrectable ECC error or parity error occurs on the mirrored channel before an uncorrectable ECC error or parity error on the other channel can be resolved, the Intel QuickPath Memory Controller will hang without an uncorrectable ECC or parity error being logged.
- Page 26 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround: Software should not disable Thermal Monitor during processor operation.
- Page 27 C6 entry may be cleared. Provided machine check exceptions are enabled, the machine check exception handler can log any uncorrectable TLB errors prior to core C6 entry. The TLB marks all detected errors as uncorrectable. Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 28 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
- Page 29 However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially available software/system. Workaround: None identified.
- Page 30 Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset (EN_FIXED_CTR{0, 1, 2} may be enabled). Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 31 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially available software. Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
- Page 32 Before programming the performance event select registers, IA32_PERFEVTSELx MSR (186H – 189H), the internal monitoring hardware must be cleared. This is accomplished by first disabling, saving valid events and clearing from the select Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 33 1 (OTHER): NT Stores to Local DRAM are counted when they should not have been. Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. Intel® Xeon® Processor 5600 Series Specification Update, March 2010...
- Page 34 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 35 ASR_PRESENT was intended to allow low power self refresh with DRAM that does not support automatic self refresh. Workaround: It is possible for Intel provided BIOS reference code to contain a workaround for this erratum. Please refer to the latest version of the BIOS memory Reference Code and release notes.
- Page 36 PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
- Page 37 Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
- Page 38 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: • Intel Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bits[2] = ‘0)
- Page 39 The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 40 The “Form” address associated with the LBR (Last Branch Record), BTM (Branch Trace Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an EIST (Enchanced Intel® SpeedStep Technology) transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling.
- Page 41 Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel Turbo Boost Technology processor capabilities may report erroneous results. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status:...
- Page 42 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status:...
- Page 43 Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a segment boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround:...
-
Page 44: Specification Changes
The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet Volumes 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M •... -
Page 45: Specification Clarifications
The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet Volume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M •... -
Page 46: Documentation Changes
The Documentation Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5600 Series Datasheet Volume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M •...