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Intel Xeon 3500 Series Datasheet

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Processor 3500 Series
Intel
Xeon
Datasheet, Volume 1
July 2009
Document Number: 321332-002

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Summary of Contents for Intel Xeon 3500 Series

  • Page 1 ® ® Processor 3500 Series Intel Xeon Datasheet, Volume 1 July 2009 Document Number: 321332-002...
  • Page 2 The Intel® Xeon® Processor 3500 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

  • Page 3: Table Of Contents

    ® ® Intel Xeon Processor 3500 Series Land Listing ............ 37 Intel Xeon Processor 3500 Series Land Assignments ..........37 4.1.1 Land Listing by Land Name ..............38 4.1.2 Land Listing by Land Number ..............56 Signal Definitions ....................75 Signal Definitions ....................
  • Page 4 Baseboard Power Header Placement Relative to Processor Socket......103 Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) ....104 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) ....104 Boxed Processor Fan Heatsink Set Points ............105 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 5 Power On Configuration Signal Options..............93 Coordination of Thread Power States at the Core Level ........... 94 Processor S-States .................... 96 Fan Heatsink Power and Signal Specifications............103 Fan Heatsink Power and Signal Specifications............105 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 6 — Intel Interconnect Built In Self Test text processing operations ® (Intel IBIST) toolbox built-in • Power Management capabilities • 1366-land Package • System Management mode • ECC and DCA (Direct Cache Access) Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 7: Revision History

    Revision History Revision Description Date Number 321332-001 • Public release March 2009 • Added Processor Information for W3580, W3550 July 2009 § Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 8 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 9: Introduction

    ® Interconnect (Intel QPI) Note: In this document the Intel Xeon Processor 3500 Series will be referred to as “the processor.” The processor is optimized for performance with the power efficiencies of a low-power microarchitecture. This document provides DC electrical specifications, differential signaling specifications,...

  • Page 10: Terminology

    • Intel® Xeon® Processor 3500 Series — The entire product, including processor substrate and integrated heat spreader (IHS). • 1366-land LGA package — The Intel® Xeon® Processor 3500 Series is available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted on a land grid array substrate with an integrated heat spreader (IHS).

  • Page 11: References

    Reference # Notes Intel® Xeon® Processor 3500 Series Specification Update 321333 Intel® Xeon® Processor Series Datasheet, Volume 2 321344 Intel® Xeon® Processor 3500 Series and LGA1366 Socket 321461 Thermal and Mechanical Design Guide Note: Document is available publicly at http://www.intel.com. §...
  • Page 12 Introduction Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 13: Electrical Specifications

    Intel QPI Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used.

  • Page 14: Vcc, Vtta, Vttd, Vddq Decoupling

    The processor core, Intel QPI, and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing.

  • Page 15: Voltage Identification Definition

    1.51875 0.95000 1.51250 0.94375 1.50625 0.93750 1.50000 0.93125 1.49375 0.92500 1.48750 0.91875 1.48125 0.91250 1.47500 0.90625 1.46875 0.90000 1.46250 0.89375 1.45625 0.88750 1.45000 0.88125 1.44375 0.87500 1.43750 0.86875 1.43125 0.86250 1.42500 0.85625 Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 16 1.21875 0.65000 1.21250 0.64375 1.20625 0.63750 1.20000 0.63125 1.19375 0.62500 1.18750 0.61875 1.18125 0.61250 1.17500 0.60625 1.16875 0.60000 1.16250 0.59375 1.15625 0.58750 1.15000 0.58125 1.14375 0.57500 1.13750 0.56875 1.13125 0.56250 1.12500 0.55625 Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 17: Reserved Or Unused Signals

    A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 18: Signal Groups

    Single Ended Asynchronous Bi-directional PECI Single Ended Analog Input COMP0, QPI_CMP[0], DDR_COMP[2:0] Single ended Asynchronous GTL Bi- PROCHOT# directional Single ended Asynchronous GTL Output THERMTRIP# Single ended CMOS Input/Output VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] VTT_VID[4:2] Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 19: Test Access Port (Tap) Connection

    Two copies of each signal may be required with each driving a different voltage level. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 20: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 21: Input Device Hysteresis

    Although the processor contains protective circuitry to resist damage from Electro- Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 22: Processor Dc Specifications

    (T as specified in Chapter 6, CASE “Thermal Specifications”), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 23: Dc Voltage And Current Specification

    V loadline. Refer to Figure 2-3 for details. CC_MAX CC_MAX This spec is based on a processor temperature, as reported by the DTS, of less than or equal to Tcontrol-25. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 24 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 25: Vcc Static And Transient Tolerance Load Lines

    VID – 0.0120 VID – 0.0435 VID + 0.0135 VID – 0.0180 VID – 0.0495 VID + 0.0075 VID – 0.0240 VID – 0.0555 VID + 0.0015 VID – 0.0300 VID – 0.0615 Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 26 2. The loadlines specify voltage limits at the die measured at the VTT_SENSE and VSS_SENSE_VTT lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VTT_SENSE and VSS_SENSE_VTT lands. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 27: Vtt Static And Transient Tolerance Load Line

    Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 28: Reset# Signal Dc Specifications

    For Vin between 0 V and V . Measured when the driver is tristated. and V may experience excursions above V This spec applies to VCCPWRGOOD and VTTPWRGOOD This specification applies to VDDPWRGOOD Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 29: Vcc Overshoot Specification

    VCC_SENSE and VSS_SENSE lands. Table 2-16. V Overshoot Specifications Symbol Parameter Units Figure Notes Magnitude of V overshoot above VID — OS_MAX Time duration of V overshoot above VID — µs OS_MAX Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 30: Die Voltage Validation

    VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. § Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 31: Package Mechanical Specifications

    • Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 32: Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 2) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 33: Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 2) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 34: Processor Component Keep-Out Zones

    The processor can be inserted into and removed from an LGA1366 socket 15 times. The socket should meet the LGA1366 requirements detailed in the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 35: Processor Mass Specification

    Substrate Lands Gold Plated Copper Processor Markings Figure 3-4 shows the topside markings on the processor. This diagram is to aid in the identification of the processor. Figure 3-4. Processor Top-Side Markings Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 36: Processor Land Coordinates

    Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-5. Processor Land Coordinates and Quadrants (Bottom View) § Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 37: Intel Xeon Processor 3500 Series Land Listing

    This section provides sorted land list in Table 4-1 Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 38: Land Listing By Land Name

    DDR0_DQ[35] CMOS DDR0_CLK_N[3] CLOCK DDR0_DQ[36] CMOS DDR0_CLK_P[0] CLOCK DDR0_DQ[37] CMOS DDR0_CLK_P[1] CLOCK DDR0_DQ[38] CMOS DDR0_CLK_P[2] CLOCK DDR0_DQ[39] CMOS DDR0_CLK_P[3] CLOCK DDR0_DQ[4] CMOS DDR0_CS#[0] CMOS DDR0_DQ[40] CMOS DDR0_CS#[1] CMOS DDR0_DQ[41] CMOS DDR0_CS#[4] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 39 DDR0_DQS_N[4] CMOS DDR0_ODT[1] CMOS DDR0_DQS_N[5] CMOS DDR0_ODT[2] CMOS DDR0_DQS_N[6] CMOS DDR0_ODT[3] CMOS DDR0_DQS_N[7] CMOS DDR0_RAS# CMOS DDR0_DQS_N[8] CMOS DDR0_RESET# CMOS DDR0_DQS_P[0] CMOS DDR0_WE# CMOS DDR0_DQS_P[1] CMOS DDR1_BA[0] CMOS DDR0_DQS_P[2] CMOS DDR1_BA[1] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 40 DDR1_DQ[20] CMOS DDR1_DQ[56] CMOS DDR1_DQ[21] CMOS DDR1_DQ[57] CMOS DDR1_DQ[22] CMOS DDR1_DQ[58] CMOS DDR1_DQ[23] CMOS DDR1_DQ[59] CMOS DDR1_DQ[24] CMOS DDR1_DQ[6] CMOS DDR1_DQ[25] CMOS DDR1_DQ[60] CMOS DDR1_DQ[26] CMOS DDR1_DQ[61] CMOS DDR1_DQ[27] CMOS DDR1_DQ[62] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 41 DDR1_MA[1] CMOS DDR2_CS#[1] CMOS DDR1_MA[10] CMOS DDR2_CS#[4] CMOS DDR1_MA[11] CMOS DDR2_CS#[5] CMOS DDR1_MA[12] CMOS DDR2_DQ[0] CMOS DDR1_MA[13] CMOS DDR2_DQ[1] CMOS DDR1_MA[14] CMOS DDR2_DQ[10] CMOS DDR1_MA[15] CMOS DDR2_DQ[11] CMOS DDR1_MA[2] CMOS DDR2_DQ[12] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 42 DDR2_DQ[41] CMOS DDR2_DQS_P[2] CMOS DDR2_DQ[42] CMOS DDR2_DQS_P[3] CMOS DDR2_DQ[43] CMOS DDR2_DQS_P[4] CMOS DDR2_DQ[44] CMOS DDR2_DQS_P[5] CMOS DDR2_DQ[45] CMOS DDR2_DQS_P[6] CMOS DDR2_DQ[46] CMOS DDR2_DQS_P[7] CMOS DDR2_DQ[47] CMOS DDR2_DQS_P[8] CMOS DDR2_DQ[48] CMOS DDR2_ECC[0] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 43 AN40 ISENSE Analog QPI_DRX_DP[16] AM42 PECI AH36 Asynch QPI_DRX_DP[17] AP41 PRDY# QPI_DRX_DP[18] AN39 PREQ# QPI_DRX_DP[19] AP38 PROCHOT# AG35 QPI_DRX_DP[2] AV36 PSI# CMOS QPI_DRX_DP[3] AW36 QPI_CLKRX_DN AR42 QPI_DRX_DP[4] BA36 QPI_CLKRX_DP AR41 QPI_DRX_DP[5] AW37 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 44 AD42 RSVD QPI_DTX_DP[13] AC43 RSVD QPI_DTX_DP[14] AD40 RSVD QPI_DTX_DP[15] AC41 RSVD QPI_DTX_DP[16] AC39 RSVD QPI_DTX_DP[17] AB39 RSVD QPI_DTX_DP[18] AD38 RSVD QPI_DTX_DP[19] AE40 RSVD QPI_DTX_DP[2] AK37 RSVD QPI_DTX_DP[3] AJ38 RSVD QPI_DTX_DP[4] AH40 RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 45 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 46 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD AV35 RSVD RSVD AV42 RSVD AM36 RSVD AV43 RSVD AM38 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD AW39 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 47 RSVD AK30 RSVD AK31 RSVD AK33 RSVD AL12 RSVD AL13 RSVD AL15 RSVD AL16 RSVD AL18 RSVD AL19 RSVD AL21 RSVD AL24 RSVD AL25 RSVD AL27 RSVD AL28 RSVD AL30 RSVD AL31 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 48 AN21 AR34 AN24 AT10 AN25 AT12 AN27 AT13 AN28 AT15 AN30 AT16 AN31 AT18 AN33 AT19 AN34 AT21 AP12 AT24 AP13 AT25 AP15 AT27 AP16 AT28 AP18 AT30 AP19 AT31 AP21 AT33 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 49 AV15 AY24 AV16 AY25 AV18 AY27 AV19 AY28 AV21 AY30 AV24 AY31 AV25 AY33 AV27 AY34 AV28 AV30 BA10 AV31 BA12 AV33 BA13 AV34 BA15 BA16 AW10 BA18 AW12 BA19 AW13 BA24 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 50 Asynch VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VID[0]/MSID[0] AL10 CMOS VDDQ VID[1]/MSID[1] CMOS VDDQ VID[2]/MSID[2] CMOS VDDQ VID[3]/CSC[0] AM10 CMOS VDDQ VID[4]/CSC[1] AN10 CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 51 AK26 AK29 AC36 AK32 AK34 AK39 AK43 AD11 AD33 AD37 AL11 AD41 AL14 AD43 AL17 AE39 AL20 AL22 AF35 AL23 AF38 AL26 AF41 AL29 AL32 AG11 AL35 AL36 AG33 AL37 AG43 AL42 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 52 AN23 AT11 AN26 AT14 AN29 AT17 AT20 AN32 AT22 AN35 AT23 AN37 AT26 AN41 AT29 AT32 AT35 AP10 AT38 AP11 AT41 AP14 AP17 AP20 AP22 AU11 AP23 AU14 AP26 AU17 AP29 AU20 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 53 AV14 AV17 BA11 AV20 BA14 AV22 BA17 AV23 BA20 AV26 BA26 AV29 BA29 AV32 AV39 BA35 BA39 AV41 AW11 AW14 AW17 AW20 AW22 AW23 AW26 AW29 AW32 AW35 AY11 AY14 AY17 AY20 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 54 Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 33 of 36) (Sheet 34 of 36) Land Buffer Land Buffer Land Name Direction Land Name Direction Type Type Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 55 AF33 VTTD AE34 VTTA AF34 VTTD AE35 VTTA AG34 VTTD VTTD AA10 VTTD VTTD AA11 VTTD AF36 VTTD AA33 VTTD AF37 VTTD AB10 VTTD VTTD AB11 VTTD VTTD AB33 VTTPWRGOOD AB35 Asynch Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 56: Land Listing By Land Number

    VDDQ DDR_COMP[2] Analog AA10 VTTD AC10 VTTD AA11 VTTD AC11 VTTD AA33 VTTD RSVD AA34 AC33 VTTD AA35 DDR1_DQ[4] CMOS AC34 VTTD AA36 DDR1_DQ[1] CMOS AC35 VTTD AA37 DDR1_DQ[0] CMOS AC36 AA38 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 57 VTTD AD41 AF37 VTTD AD42 QPI_DTX_DP[12] AF38 AD43 AF39 QPI_DTX_DP[1] RSVD RSVD RSVD AF40 QPI_DTX_DN[19] RSVD AF41 RSVD AF42 QPI_CLKTX_DN VTTD AF43 QPI_DTX_DP[10] RSVD AE10 VTTA RSVD AE11 VTTA VTT_VID3 CMOS VTTD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 58 RSVD RSVD AH33 RSVD AH34 AK10 AH35 BCLK_DN CMOS AK11 AH36 PECI Asynch AK12 AH37 AK13 AH38 QPI_DTX_DN[0] AK14 AH39 AK15 RSVD AK16 AH40 QPI_DTX_DP[4] AK17 AH41 QPI_DTX_DP[6] AK18 AH42 QPI_DTX_DN[6] AK19 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 59 RSVD RSVD AL40 RSVD RSVD AL41 RSVD RSVD AL42 ISENSE Analog AL43 QPI_CMP[0] Analog RSVD RSVD AL10 VID[0]/MSID[0] CMOS AL11 RSVD AL12 VID[1]/MSID[1] CMOS AL13 RSVD AL14 AM10 VID[3]/CSC[0] CMOS AL15 AM11 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 60 AM38 RSVD AN34 AM39 AN35 RSVD AN36 RSVD AM40 QPI_DRX_DN[15] AN37 AM41 QPI_DRX_DN[16] AN38 RSVD AM42 QPI_DRX_DP[16] AN39 QPI_DRX_DP[18] AM43 QPI_DRX_DN[14] RSVD AN40 QPI_DRX_DP[15] RSVD AN41 RSVD AN42 QPI_DRX_DN[13] RSVD AN43 QPI_DRX_DP[14] Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 61 AP27 AR23 AP28 AR24 AP29 AR25 RSVD AR26 AP30 AR27 AP31 AR28 AP32 AR29 AP33 AP34 AR30 AP35 AR31 AP36 AR32 AP37 AR33 AP38 QPI_DRX_DP[19] AR34 AP39 QPI_DRX_DN[18] AR35 RSVD AR36 RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 62 AT19 AU15 RSVD AU16 AT20 AU17 AT21 AU18 AT22 AU19 AT23 RSVD AT24 AU20 AT25 AU21 AT26 AU22 AT27 AU23 AT28 AU24 AT29 AU25 RSVD AU26 AT30 AU27 AT31 AU28 AT32 AU29 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 63 AV10 RSVD AV11 RSVD AV12 AV13 AV14 AW10 AV15 AW11 AV16 AW12 AV17 AW13 AV18 AW14 AV19 AW15 RSVD AW16 AV20 AW17 AV21 AW18 AV22 AW19 AV23 RSVD AV24 AW20 AV25 AW21 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 64 AY41 RSVD AY42 RSVD RSVD RSVD AY10 RSVD AY11 AY12 DDR0_CS#[1] CMOS AY13 DDR0_ODT[2] CMOS AY14 VDDQ AY15 DDR0_WE# CMOS AY16 DDR1_MA[13] CMOS AY17 DDR0_CS#[4] CMOS AY18 DDR0_BA[0] CMOS AY19 VDDQ RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 65 RSVD DDR0_CAS# CMOS DDR0_DQ[32] CMOS RSVD DDR0_DQ[36] CMOS RSVD VDDQ VDDQ RSVD DDR2_WE# CMOS RSVD DDR1_CS#[4] CMOS BA10 DDR1_BA[0] CMOS BA11 DDR0_CLK_N[1] CLOCK BA12 BPM#[2] BA13 VDDQ BA14 DDR1_CLK_P[0] CLOCK BA15 RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 66 BPM#[4] DDR1_DQ[38] CMOS DDR2_ODT[3] CMOS DDR1_DQS_N[4] CMOS DDR1_ODT[0] CMOS DDR1_CS#[0] CMOS DDR2_CS#[5] CMOS VDDQ DDR1_ODT[2] CMOS DDR1_CS#[5] CMOS DDR2_ODT[2] CMOS VDDQ RSVD RSVD DDR2_RAS# CMOS RSVD VDDQ DDR1_CAS# CMOS DDR0_CLK_P[1] CLOCK RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 67 DDR0_DQ[18] CMOS DDR0_DQ[19] CMOS DDR1_DQ[34] CMOS DDR2_DQ[25] CMOS DDR0_DQS_P[2] CMOS DDR1_DQS_P[4] CMOS DDR0_DQ[23] CMOS DDR1_DQ[33] CMOS DDR0_DQ[22] CMOS DDR1_DQ[32] CMOS DDR1_DQ[35] CMOS DDR0_DQ[34] CMOS DDR1_DQ[39] CMOS DDR1_DQ[36] CMOS RSVD DDR1_ODT[3] CMOS RSVD Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 68 DDR1_DQS_N[8] CMOS DDR1_ECC[7] CMOS RSVD DDR1_ECC[3] CMOS DDR2_ECC[0] CMOS DDR1_DQ[24] CMOS RSVD DDR1_DQ[29] CMOS DDR2_DQ[29] CMOS DDR1_DQ[42] CMOS DDR1_DQ[23] CMOS DDR2_DQ[24] CMOS DDR2_DQ[27] CMOS DDR0_DQS_N[2] CMOS RSVD DDR2_DQ[28] CMOS RSVD DDR1_DQ[43] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 69 CMOS DDR1_MA[6] CMOS DDR2_MA[5] CMOS VDDQ RSVD RSVD RSVD VDDQ DDR2_ECC[5] CMOS RSVD DDR2_ECC[4] CMOS DDR1_MA[4] CMOS DDR1_DQ[27] CMOS RSVD DDR0_DQS_N[5] CMOS DDR1_DQ[28] CMOS DDR1_DQ[31] CMOS DDR1_DQ[19] CMOS DDR1_DQ[22] CMOS DDR1_DQ[26] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 70 DDR0_DQ[43] CMOS VDDQ DDR2_DQ[45] CMOS RSVD DDR2_ODT[0] CMOS RSVD DDR1_CLK_N[2] CLOCK VDDQ DDR0_DQ[47] CMOS DDR2_CLK_P[1] CLOCK VDDQ DDR2_CLK_N[3] CLOCK DDR2_CLK_P[3] CLOCK DDR_VREF Analog VDDQ DDR2_MA[8] CMOS DDR2_BA[2] CMOS DDR2_CKE[3] CMOS DDR1_MA[3] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 71 CMOS DDR2_DQS_P[6] CMOS DDR2_DQ[48] CMOS DDR0_DQ[49] CMOS DDR0_DQ[53] CMOS DDR2_DQ[50] CMOS DDR1_DQ[20] CMOS DDR2_DQ[54] CMOS DDR2_DQ[21] CMOS DDR0_DQS_P[6] CMOS DDR1_DQ[14] CMOS DDR0_DQS_N[6] CMOS DDR1_DQ[15] CMOS DDR1_DQ[11] CMOS DDR1_DQ[12] CMOS RSVD DDR1_DQ[13] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 72 CMOS DDR0_DQ[7] CMOS DDR2_DQ[7] CMOS DDR0_DQS_P[0] CMOS DDR2_DQ[13] CMOS DDR1_DQ[51] CMOS DDR0_DQ[62] CMOS DDR2_DQ[60] CMOS DDR2_DQ[61] CMOS DDR0_DQ[1] CMOS DDR2_DQS_N[7] CMOS RSVD RSVD DDR0_DQ[60] CMOS DDR2_DQ[59] CMOS RSVD RSVD RSVD DDR2_DQ[62] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 73 CMOS DDR1_DQ[7] CMOS DDR2_DQ[12] CMOS RSVD DDR0_DQ[63] CMOS DDR1_DQ[6] CMOS DDR0_DQ[4] CMOS DDR0_DQ[0] CMOS RSVD DDR0_DQ[5] CMOS DDR_COMP[1] Analog DDR1_DQ[61] CMOS DDR1_DQS_P[7] CMOS DDR1_DQ[56] CMOS DDR1_DQS_N[7] CMOS DDR1_DQ[57] CMOS § DDR1_DQ[63] CMOS Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 74 ® ® Intel Xeon Processor 3500 Series Land Listing Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 75: Signal Definitions

    COMP0 Impedance compensation must be terminated on the system board using a precision resistor. QPI_CLKRX_DN Intel QPI received clock is the input clock that corresponds to the received data. QPI_CLKRX_DP QPI_CLKTX_DN Intel QPI forwarded clock sent with the outbound data.
  • Page 76 TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTLOW TESTLOW must be connected to ground through a resistor for proper processor operation. Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 77 VTTPWRGOOD. Power for analog portion of the integrated memory controller, QPI and Shared Cache. Power for the digital portion of the integrated memory controller, QPI and Shared Cache. Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...
  • Page 78 The signal must then transition monotonically to a high state. Note that it is not valid for VTTPWRGOOD to be deasserted while VCCPWRGOOD is asserted. Notes: DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2. § Intel® Xeon® Processor 3500 Series Datasheet, Volume 1...

  • Page 79: Thermal Specifications

    The fan speed control algorithm can be updated to utilize the additional information to optimize acoustics. To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor thermal solution must deliver the specified thermal solution performance in response to the DTS sensor value.

  • Page 80: Processor Thermal Specifications

    Processor idle power is specified under the lowest possible idle state: processor package C6 state. Achieving processor package C6 state is not supported by all chipsets. See Intel X58 Express Chipset specifications for more details. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 81: Processor Thermal Profile

    59.2 65.2 46.6 53.1 59.5 65.6 47.0 53.5 59.9 66.0 47.4 53.8 60.3 66.4 47.8 54.2 60.7 66.8 48.1 54.6 61.1 67.1 48.5 55.0 61.4 67.5 48.9 55.4 61.8 67.9 49.3 55.7 Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 82 = 0.19 + (43.2 – T ) * 0.013 AMBIENT This column can be expressed as a function of T by the following equation: AMBIENT = 0.19 + (43.2 – T ) * 0.0077 AMBIENT Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 83: Thermal Metrology

    C3: Max = 2.3 mm, Min = 2.2 mm C4: Max = 2.3 mm, Min = 2.2 mm. Refer to the appropriate Thermal and Mechanical Design Guide (see Section 1.2) for instructions on thermocouple installation on the processor TTV package. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 84: Processor Thermal Features

    6.2.1 Processor Temperature A new feature in the Intel Xeon Processor 3500 Series is a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted. The TCC activation...
  • Page 85 Thermal Specifications The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. The following sections provide more details on the different TCC mechanisms used by the Intel Xeon Processor 3500 Series. 6.2.2.1 Frequency/VID Control When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures reported via PECI may not equal zero when PROCHOT# is activated, see Section 6.3...

  • Page 86: Frequency And Voltage Ordering

    TCC activation point. Once below the TCC activation temperature, TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio/VID state. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 87: Thermtrip# Signal

    Unless immediate action is taken to resolve the failure, the processor will probably reach the Thermtrip temperature (see Section 6.2.3 Thermtrip Signal) within a short time. To prevent possible permanent silicon damage, Intel recommends removing power from the processor within ½ second of the Critical Temperature Flag being set 6.2.2.5...

  • Page 88: Platform Environment Control Interface (Peci)

    Introduction The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control.

  • Page 89: Peci Specifications

    RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 90: Storage Conditions Specifications

    ABSOLUTE STORAGE moisture barrier bags or desiccant. Intel® branded board products are certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40°C to 70°C & Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28°C) Post board attach storage temperature limits are not specified for non-Intel®...
  • Page 91 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by T and customer shelf life in applicable intel® box and bags. SUSTAINED § Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 92 Thermal Specifications Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 93: Features

    Chapter 2. Note that request to execute BIST is not selected by hardware but is passed across the Intel QPI link during initialization. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor;...

  • Page 94: Thread And Core Power State Descriptions

    MWAIT instruction. RESET# will cause the processor to initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal ® state or the C1 state. See the Intel 64 and IA-32 Architectures Software Developer's Manuals, Volume III: System Programmer's Guide for more information.

  • Page 95: Package Power State Descriptions

    Because the core’s caches are flushed, the processor keeps the core in the C3 state when the processor detects a snoop on the Intel QPI Link or when another logical processor in the same package accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of an interrupt.

  • Page 96: Sleep States

    Features If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and for processors with an integrated memory controller, the DRAM will be put into self- refresh. 7.2.2.4 Package C6 State The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C6 state.

  • Page 97: Enhanced Intel Speedstep Technology

    • The processor controls voltage ramp rates internally to ensure smooth transitions. • Low transition latency and large number of transitions possible per second: — Processor core (including shared cache) is unavailable for less than 5 µs during the frequency transition. § Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 98 Features Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 99: Boxed Processor Specifications

    Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.

  • Page 100: Mechanical Specifications

    Airspace requirements are shown in Figure 8-7 Figure 8-8. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning. Figure 8-2. Space Requirements for the Boxed Processor (side view) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 101: Space Requirements For The Boxed Processor (Top View)

    Space Requirements for the Boxed Processor (top view) Notes: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 8-4. Space Requirements for the Boxed Processor (overall view) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 102: Boxed Processor Fan Heatsink Weight

    Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. +12 V 0.100" pitch, 0.025" square pin width. SENSE CONTROL Match with straight pin, friction lock header on mainboard. 1 2 3 4 Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 103: Thermal Specifications

    The air temperature entering the fan should be kept below 40 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 104: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)

    Boxed Processor Specifications Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) Figure 8-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) Intel® Xeon® Processor 3500 Series Datasheet Volume 1...

  • Page 105: Variable Speed Fan

    When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. Recommended maximum internal chassis temperature for worst-case operating environment. 1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink. Intel® Xeon® Processor 3500 Series Datasheet Volume 1...
  • Page 106 As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.

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