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Intel Xeon 5500 Series Specification Update

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Intel® Xeon® Processor 5500
Series
Specification Update
February 2014
Reference Number: 321324-017

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Summary of Contents for Intel Xeon 5500 Series

  • Page 1 Intel® Xeon® Processor 5500 Series Specification Update February 2014 Reference Number: 321324-017...
  • Page 2 LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

  • Page 3: Table Of Contents

    Contents Revision History ....................... 5 Preface ..........................7 Summary Tables of Changes ..................10 Identification Information ....................20 Errata ..........................27 Specification Changes....................79 Specification Clarifications ................... 80 Documentation Changes ....................81 § Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 4 Intel® Xeon® Processor 5500 Series Specification Update, February 2014...

  • Page 5: Revision History

    -014 Added Errata AAK158 through AAK160 January 2011 321324 -015 Added Errata AAK161 through AAK166 April 2011 321324 -016 Added Errata AAK167-AAK171 August 2013 322324 -017 Added Errata AAK172-AAK181 February 2014 Intel® Xeon® Processor 5500 Series Specification Update, February 2014...

  • Page 6: Preface

    This document may also contain information that was not previously published. Affected Documents Document Number/ Document Title Location Intel® Xeon® Processor 5500 Series Datasheet Volume 1 and 2 321321 & 321322 Related Documents Document Number/ Document Title Location http://www.intel.com/...
  • Page 7 Nomenclature Errata are design defects or errors. These may cause the Intel® Xeon® Processor 5500 Series behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

  • Page 8: Summary Tables Of Changes

    The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® Xeon® Processor 5500 Series product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 9 Point Exception AAK27. No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1 Intel® QuickPath Interconnect (Intel® QPI) Memory Controller May Hang If AAK28. No Fix Uncorrectable ECC Errors Occur on Both Channels in Mirror Channel Mode Intel® Xeon® Processor 5500 Series...
  • Page 10 After VM Entry, Instructions May Incorrectly Operate as if CS.D=0 AAK54. Fixed An Intel QPI Link in a DP Configuration May Hang Due to Flit Prioritization AAK55. Fixed Spurious Machine Check Error May Occur When Logical Processor is Woken Up AAK56.
  • Page 11 PEBS Field “Data Linear Address” is Not Sign Extended to 64 Bits AAK80. No Fix Core C6 May Not Operate Correctly in the Presence of Bus Locks USB 1.1 ISOCH Audio Glitches With Intel QPI L1 and Package C6 in a DP AAK81. No Fix Configuration Intel®...
  • Page 12 Enabled AAK96. No Fix ISSUEONCE Bit in MC_SCRUB_CONTROL Register Does Not Work Correctly Unexpected Intel QPI Link Behavior May Occur When a CRC Error Happens AAK97. No Fix During L0s Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is AAK98.
  • Page 13 AAK123. No Fix a System Hang AAK124. Plan Fix Intel QPI Link in a DP Configuration May Hang Due to Back-Back CRC Errors AAK125. Plan Fix tRP Timing Violations May be Observed Near a Self Refresh Entry AAK126. Plan Fix Concurrent Updates to a Segment Descriptor May be Lost AAK127.
  • Page 14 Cache May be Over Counted AAK155. No Fix VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Intel QPI Lane May Be Dropped During Full Frequency Deskew Phase of AAK156. No Fix Training PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have AAK157.
  • Page 15 A First Level Data Cache Parity Error May Result in Unexpected Behavior Executing The GETSEC Instruction While Throttling May Result in a Processor AAK181. No Fix Hang Notes: 1. For this stepping of the product BIOS workaround is not available. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 16 None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS AAK1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes Number DOCUMENTATION CHANGES None for this revision of the specification update. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...

  • Page 17: Identification Information

    Identification Information Component Identification via Programming Interface The Intel® Xeon® Processor 5500 Series stepping can be identified by the following register contents: Extended Extended Processor Family Model Stepping Reserved Reserved Family Model Type Code Number 31:28 27:20 19:16 15:14 13:12...
  • Page 18 Component Marking Information Intel® Xeon® Processor 5500 Series stepping can be identified by the following component markings: Figure 1. Processor Top-side Markings (Example) Table 1. Intel® Xeon® Processor 5500 Series Identification Core Frequency (GHz) / Available bins Cache S-Spec Intel® QuickPath of Intel®...
  • Page 19 1066 MHz; however, this processor has additional support to override the integrated memory controller frequency. Column indicates the number of frequency bins (133.33 MHz) of Intel® Turbo Boost Technology that are available for 4, 3, 2, or 1 cores active respectively.
  • Page 20 AND’ed feature flag values, then the processors with the numerically lower CPUID should be selected as the BSP. 6. Intel requires that the processor microcode update be loaded on each processor operating within the system. Any processor that does not have the proper microcode update loaded is considered by Intel to be operating out of specification.

  • Page 21: Errata

    The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled “Switching to Protected Mode”...
  • Page 22 CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAK5. The Processor May Report a #TS Instead of a #GP Fault...
  • Page 23 In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing. If the exception Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 24 Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to “Procedure Calls For Block-Structured Languages” in Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Intel® Xeon® Processor 5500 Series...
  • Page 25 Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 26 Workaround: Code pages should not be mapped with uncacheable and cacheable memory types at the same time. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 27 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 28 Channel Mode Problem: If an uncorrectable ECC error occurs on the mirrored channel before an uncorrectable ECC error on the other channel can be resolved, the Intel QPI Memory Controller will hang without an uncorrectable ECC error being logged. Implication: The processor may hang and not report the error when uncorrectable ECC errors occur in close proximity on both channels in a mirrored channel pair.
  • Page 29 For the steppings affected, see the Summary Tables of Changes. AAK30. Intel QPI Memory Controller tTHROT_OPREF Timings May be Violated During Self Refresh Entry Problem: During self refresh entry, the memory controller may issue more refreshes than permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1,2}_REFRESH_TIMING CSR).
  • Page 30 Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again. Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround: Software should not disable Thermal Monitor during processor operation.
  • Page 31 This erratum will occur when the following additional conditions are also met. • The MMX store instruction must be the first MMX instruction to operate on x87 FPU state (that is, the x87 FP tag word is not already set to 0x0000). Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 32 USB 1.1 ISOCH Audio Glitches with Intel QPI Locks and Deep C-States Problem: An interrupt directed at a Core in C3 or C6 that collides with an Intel QPI Lock sequence may delay ISOCH transactions to DRAM long enough to underrun USB 1.1 buffers.
  • Page 33 Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 34 L1, while the Link Level Retry (LLR) buffer of the Intel QPI link slave is full, a priority conflict between flits occurs. To begin the state transition, the Intel QPI master sends the Enter.L1 flit. The Intel QPI link slave sends an LLR.Idle flit because the LLR buffer is full and because it has higher...

  • Page 35: Power States

    MOVNTDQA then this erratum does not apply. Workaround: Software that requires a locked instruction to fence subsequent executions of MOVNTDQA should insert an LFENCE instruction before the first execution of Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 36 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
  • Page 37 DIMM ID of the DIMM that detected error and not necessarily the DIMM that was targeted by the error injection settings. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 38 80000004H, the return values will contain the brand string with an additional zero between the processor number and the @ symbol. (For example: Intel® Xeon® CPU nnn0 @ x.xx GHz where nnn is a processor number and x.xx is the frequency) Implication: When this erratum occurs, the processor will report the incorrect brand string.
  • Page 39 However, the pending interrupt event will not be cleared. Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the external interrupt. Intel has not observed this erratum with any commercially available software/system. Workaround: None identified.
  • Page 40 The PEBS Data Linear Address field may not have the sign bit correctly extended to bits [63:48]. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 41 Package C-state Exit with Intel QPI L1 Mode Disabled Problem: If the processor is resident in package C3 or C6 for greater than 100 ms and Intel QPI link L1 mode is disabled, it is possible for Turbo Boost input parameters to be incorrect.
  • Page 42 Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset (EN_FIXED_CTR{0, 1, 2} may be enabled). Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 43 0x0150. This hang condition requires a specific sequence of instructions coincident with the P-state or ACPI event. Implication: When this erratum occurs, the processor will unexpectedly hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 44 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially available software. Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
  • Page 45 When an Intel QPI agent requests L0s entry while a CRC (Cyclic Redundancy Check) error occurs during this flit or on the flit just before it, the requesting Intel QPI agent may enter L0s and turn its drivers off. During this time noise on the link may be interpreted as an Intel QPI command by the remote Intel QPI agent, and may result in unexpected behavior.
  • Page 46 Due to this erratum, the system may exhibit higher than expected idle power due to low C6 residency. Workaround: It possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 47 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
  • Page 48 MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL field are not in increasing populated DDR3 rank order. Workaround: It is possible for Intel provided BIOS reference code to contain a workaround for this erratum. Please refer to the latest version of BIOS Memory Reference Code and release notes.
  • Page 49 Summary Tables of Changes. AAK116. A String Instruction that Re-maps a Page May Encounter an Unexpected Page Fault An unexpected page fault (#PF) may occur for a page under the following conditions: Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 50 Implication: Software may see an unexpected page fault that indicates that there is no translation for the page. Intel has not observed this erratum with any commercially available software or system. Workaround: Software should not update the paging structures with a string instruction that accesses pages mapped the modified paging structures.
  • Page 51 PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
  • Page 52 Implication: In the unlikely event, if two CRC errors occur on the same Intel QPI link in very close proximity, under certain conditions, the Intel QPI link may hang. Intel has not observed this erratum with any commercial system.
  • Page 53 Workaround: It is possible for the BIOS to contain a workaround for this erratum, along with the latest Intel® 5500 Platform for 2S platforms CPU/Intel QPI/Memory Reference Code. Status: For the steppings affected, see the Summary Tables of Changes AAK130.
  • Page 54 WMM must be disabled if Demand and/or Patrol Scrubs are enabled. Memory Reference code provided by Intel disables WMM if Demand scrubs are enabled by writing the WMM threshold value to its maximum value of 1FH in WMENTRYTHRESHOLD bits [9:5], and WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0,1,2}_WAQ_PARAMS register.
  • Page 55 Adaptive Thermal Throttling. Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch “From” addresses for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E, or Adaptive Thermal Throttling. Workaround: None identified.
  • Page 56 If Intel Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
  • Page 57 Core C6 state, it is possible that an interrupt may be dropped. Implication: Due to this erratum, an interrupt may be dropped. Intel has not observed this erratum with any commercially available software. Intel® Xeon® Processor 5500 Series...
  • Page 58 Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 59 REP I/O instruction. Due to this erratum, the setting of the IO_SMI bit may be lost. This may happen under a complex set of internal conditions with Intel HT Technology enabled and has not been observed with commercially available software.
  • Page 60 Intel QPI Lane May Be Dropped During Full Frequency Deskew Phase of Training Problem: A random Intel QPI Lane may be dropped during the lane deskew phase while the Intel QPI Bus is training at full frequency. Implication: When there are multiple resets after the Intel QPI Bus has reached full speed operation there is a small chance that a lane could be dropped during the deskew phase of training.
  • Page 61 The erratum applies only if the VM entry is not to IA-32e mode and is to 16-bit operation, and only if the relevant handler uses 16-bit operation. The incorrect stack pushes resulting from the erratum may cause incorrect guest operation. Intel has not observed this erratum with any commercially available software.

  • Page 62: Branch Instructions

    MSRs. (Note that documentation of the WRMSR instruction states that “Undefined or reserved bits in an MSR should be set to values previously read.”) Workaround: It is possible for the BIOS to contain a workaround for this erratum. Intel® Xeon® Processor 5500 Series Specification Update, February 2014...
  • Page 63 SMM (system-management mode) might save and restore processor state from incorrect addresses. Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially available system. Workaround: Ensure that the SMRAM state-save area is located entirely below the 4 GB address boundary.
  • Page 64 A machine check occurring during VM entry may cause the VM entry to fail. Due to this erratum, such a VM entry failure may be followed by unpredictable behavior, including a processor hang. Implication: This erratum may result in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 65 63:32. Because this erratum applies only to executions outside 64-bit mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to invalidate translations for a 64-bit guest. Intel has not observed this erratum with any commercially available software.
  • Page 66 Implication: Due to this erratum unpredictable system behavior may occur. Intel has not observed this erratum with any commercially available system. Workaround: None identified.

  • Page 67: Specification Changes

    The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5500 Series Datasheet Volume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M •...

  • Page 68: Specification Clarifications

    The Specification Clarifications listed in this section may apply to the following documents: • Intel® Xeon® Processor 5500 Series Datasheet Volume 1 & 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M •...

  • Page 69: Documentation Changes

    Note: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to become familiar with this file.
  • Page 70 Intel® Xeon® Processor 5500 Series Specification Update, February 2014...

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