Condition Registers; Transition Filters; Event Registers; Enable Registers - Keithley 2002 User Manual

IEEE-488 Reference

3.7.1 Condition registers

As shown in the illustrations, all status register sets, except
the standard event status register set, have a condition regis-
ter. A condition register is a real-time read-only register that
constantly updates to reflect the current operating conditions
of the instrument. For example, while a calculation is being
performed, bit B9 (Calc) of the Operation Condition Regis-
ter is set. When the calculation is completed, bit B9 clears.
The :CONDition? query commands in the STATus Sub-
system are used to read the condition registers. See para-
graph 3.20 for details.
3.7.2 Transition filters
As shown in the illustrations, all status register sets, except
the standard event status register set, have a transition filter.
A transition filter is made up of two registers that are pro-
grammed by the user. It is used to specify which transition (0
to 1, or 1 to 0) in the corresponding condition register will set
the corresponding bit in the event register.
A filter can be programmed for positive transitions (PTR),
negative transitions (NTR) or both. When an event is pro-
grammed for a positive transition, the corresponding bit in
the event register sets when the corresponding bit in the con-
dition register changes for 0 to 1. Conversely, when pro-
grammed for a negative transition, the bit in the event register
sets when the corresponding bit in the condition register
changes from 1 to 0.
The :PTR and :NTR commands in the Status Subsystem are
used to set or clear the individual bits of the transition filter
registers, while the :PTR? and :NTR? query commands are
used to read the registers (see paragraph 3.20 for details).
Reading a transition filter register does not affect its bit
pattern.
The following operations set (1) all bits of all PTR registers
and clear (0) all bits of all NTR registers:
• Cycling power
• Sending :STATus:PRESet

3.7.3 Event registers

As shown in the illustrations, each status register set has an
event register. An event register is a latched, read-only regis-
ter whose bits are set by the corresponding condition register
and transition filter. Once a bit in an event register is set, it
remains set (latched) until the register is cleared by a specific
3-8
clearing operation. The bits of an event register are logically
ANDed with the bits of the corresponding enable register
and applied to an OR gate. The output of the OR gate is
applied to another register set or to the Status Byte Register.
The *ESR? Common Command is used to read the Standard
Event Register (see paragraph 3.10.3). All other event regis-
ters are read using the [:EVENT]? query commands in the
STATus Subsystem (see paragraph 3.20).
An event register is cleared when it is read. The following
operations clear all event registers:
• Cycling power
• Sending *CLS

3.7.4 Enable registers

As shown in the illustrations, each status register set has an
enable register. An enable register is programmed by the user
and serves as a mask for the corresponding event register. An
event bit is masked when the corresponding bit in the enable
register is cleared (0). When masked, a set bit in an event reg-
ister cannot set a bit in a following register set or in the Status
Byte Register (1 AND 0 = 0).
To use the Status Byte Register to detect events (i.e. serial
poll), you must unmask the events by setting (1) the appro-
priate bits of the enable registers.
The Standard Event Status Enable Register is programmed
and queried using the *ESE and *ESE? Common Com-
mands respectively (see paragraph 3.10.2). All other enable
registers are programmed and queried using the :ENABle
and :ENABle? commands in the STATus Subsystem (see
paragraph 3.20).
An enable register is not cleared when it is read. The Enable
registers are affected by the following operations:
• Cycling power – Clears all enable registers
• :STATus:PRESet clears the following enable registers:
Operation Event Enable Register
Questionable Event Enable Register
Measurement Event Enable Register
• :STATus:PRESet sets all bits of the following enable
registers:
Trigger Event Enable Register
Arm Event Enable Register
Sequence Event Enable Register
• *ESE 0 – Clears the Standard Event Status Enable
Register.