Figure 3-7 Arm Event Status - Keithley 2002 User Manual

To Bit B6 (Arm) of
Operation Event
Condition Register
(See Figure 3-6).
Figure 3-7
Arm event status
From ORed
Summary of
Sequence Event
Status (See
Figure 3-8).
Always
Zero
(B15)
0
(B15)
0
(B15)
0
&
OR
(B15)
Seq 1 = Sequence 1 (Set bit indicates that the
& = Logical AND
OR = Logical OR
PTR = Positive Transition Register
NTR = Negative Transition Register
Seq1
Arm
Condition Register
(B1) (B0)
(B14 - B2)
Seq1 PTR
(B1) (B0) NTR
(B14 - B2)
Seq1
Arm Event
Register
(B1) (B0)
(B14 - B2)
&
Seq1
Arm Event
Enable Register
(B1) (B0)
(B14 - B2)
2001 is in the arm layer of Sequence 1)
IEEE-488 Reference
Arm
Transition Filter
3-11