Debug Port Error Status - Toshiba TECRA M10 Maintenance Manual

2.4 System Board Troubleshooting
System BIOS Boot block processing
CPU setup
MCH initialization
ICH initialization
EC access check
setup of PIT
Initialization of ICH and Super
I/O
BIOS ROM check
F000
Problematic to BIOS ROM data.
F001 EC/KBC rewriting check
Initialization of EC
F002 Initialization of EC
Initialization of KBC
F003 Initialization failure of EC
Initialization failure of EC (HW
F004
failure)
F005 CPU setup
F006 BIOS Update check
F007 BIOS ROM check BIOS
F008 BIOS ROM check 2
F009 End of Boot Block processing
TECRA M10 Maintenance Manual (960-685)
Table 2-4 Debug port error status (1/8)
CPU
MCH(register)
ICH (register, PIT controller,
MEM I/O)
EC/KBC(EC)
BIOSROM, Super I/O
BIOSROM
EC/KBC(KBC)
BIOSROM
EC/KBC(EC,KBC)
BIOSROM
CPU
BIOSROM
EC/KBC(EC)
BIOSROM
BIOSROM
2 Troubleshooting Procedures
IS1050 (CPU Socket)
IC1200 (MCH)
IC1600 (ICH)
IC3200 (EC/KBC)
IC3001 (BIOS ROM)
IC3400 (Super I/O)
IC3001 (BIOS ROM)
IC3200 (EC/KBC)
IC3000 (BIOS ROM)
IC3200 (EC/KBC)
IC3000 (BIOS ROM)
IS1050 (CPU Socket)
IC3000 (BIOS ROM)
IC3200 (EC/KBC)
IC3000 (BIOS ROM)
IC3000 (BIOS ROM)
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