Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Datasheet page 72

Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 7 of 8)
Name
STPCLK#
TCK
TDI
TDO
TESTHI[13:0]
THERMDA
THERMDC
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCA
VCCIOPLL
VCC_SENSE
VCC_MB_
REGULATION
72
Type
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
Input
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
de-asserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
Input
known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
Input
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
Output
provides the serial output needed for JTAG specification support.
TESTHI[13:0] must be connected to the processor's appropriate power source
Input (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a
resistor for proper processor operation. See
Other Thermal Diode Anode. See
Other Thermal Diode Cathode. See
In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum T
processor junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the processor will
shut off its internal clocks (thus, halting program execution) in an attempt to
reduce the processor junction temperature. To protect the processor, its core
Output voltage (V ) must be removed following the assertion of THERMTRIP#.
CC
Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-
assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the
processor's junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 µs of the assertion of
PWRGOOD.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
Input
tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
Input receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
Input
driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to these pins is
Input
determined by the VID[5:0] pins.
Input VCCA provides isolated power for the internal processor core PLLs.
Input VCCIOPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor core power
Output (V ). It can be used to sense or measure voltage near the silicon with little
CC
noise.
This land is provided as a voltage regulator feedback sense point for V
connected internally in the processor package to the sense point land U27 as
Output
described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop
Socket 775.
Description
Section 2.5
Section 5.2.7.
Section 5.2.7.
. Assertion of THERMTRIP# (Thermal Trip) indicates the
C
for more details.
. It is
CC
Datasheet