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6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Pentium 4 processor in the 775-
land package samples the hardware configuration at reset, on the active-to-inactive transition of
RESET#. For specifications on these options, refer to
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor; for reset
purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Frequency determination functionality will exist on engineering sample processors which means
that samples can run at varied frequencies. Production material will have the bus to core ratio
locked and can only be operated at the rated frequency.
Table 6-1. Power-On Configuration Option Signals
Output tristate
Execute BIST
In Order Queue pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC Cluster ID (0-3)
Disable bus parking
Disable Hyper-Threading Technology
Symmetric agent arbitration ID
RESERVED
NOTES:
1.
Asserting this signal during RESET# will select the corresponding option.
2.
Address signals not identified in this table as configuration options should not be asserted during RESET#.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by
stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 6-1
The processor adds support for the Enhanced HALT powerdown state. Refer to
following sections.
Not all processors are capable of supporting the Enhanced HALT state. Refer to the Specification
Update to determine which processor stepping and frequencies will support the Enhanced HALT
state.
Datasheet
Configuration Option
for a visual representation of the processor low power states.
Table
6-1.
1, 2
Signal
SMI#
INIT#
A7#
A9#
A10#
A[12:11]#
A15#
A31#
BR0#
A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#
Features
Figure 6-1
and the
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