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BASIC TIMER
f
XX
f
XX
f
DIV
XX
f
XX
f
XX
u
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
10-4
Bits 3, 2
/4096
/1024
MUX
/128
/16
Figure 10-2. Basic Timer Block Diagram
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
RESET or STOP
Bit 1
Data Bus
Clear
8-Bit Up Counter
(BTCNT, Read-Only)
Start the CPU
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
OVF
(note)
RESET
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