And Logical And - Samsung S3C8275X User Manual

INSTRUCTION SET
AND
— Logical AND
AND dst,src
dst ← dst AND src
Operation:
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
AND
AND
AND
AND
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-16
dst | src
src dst
dst src
→
R1,R2
→
R1,@R2
→
01H,02H
→
01H,@02H
→
01H,#25H
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Bytes
2
3
3
R1 = 02H, R2 = 03H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
Cycles Opcode
(Hex)
4 52
6 53
6 54
6 55
6 56
Addr Mode
dst src
r r
r lr
R R
R IR
R IM