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TIMER 1
MSB
Not used for
S3C8275X/C8278X/C8274X
Timer B clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxt (sub clock)
Others = Not available
11-6
Timer B Control Register (TBCON)
E7H, Set 1, Bank 1, R/W
.7
.6
.5
.4
Figure 11-4. Timer B Control Register (TBCON)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
.3
.2
.1
.0
Timer B interrupt pending bit:
0 = No interrupt pending (when read)
1 = Interrupt is pending (when read)
Timer B interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer B counter operating enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer B counter clear bit:
0 = No affect
1 = Clear the timer B counter (when write)
LSB
Clear pending bit (when write)
No effect (when write)
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