Enable/Disable Interrupt Instructions (Ei, Di); System-Level Interrupt Control Registers; Interrupt Control Register Overview - Samsung S3C8275X User Manual

INTERRUPT STRUCTURE

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur according to the established priorities.
The system initialization routine executed after a reset must always contain an EI instruction to globally
enable the interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
•
The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
•
The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
•
The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
•
The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Control Register
Interrupt mask register
Interrupt priority register
Interrupt request register
System mode register
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
5-6
Table 5-2. Interrupt Control Register Overview
ID R/W
IMR R/W Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0−IRQ7.
IPR R/W Controls the relative processing priorities of the interrupt levels.
The seven levels of S3C8275X/C8278X/C8274X are organized
into three groups: A, B, and C. Group A is IRQ0 and IRQ1,
group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6,
and IRQ7.
IRQ R This register contains a request pending bit for each interrupt
level.
SYM R/W This register enables/disables fast interrupt processing and
dynamic global interrupt processing.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
NOTE
Function Description