Clock Generator - EUROCOM B7110 Service Manual

Clock Generator

CLOCK GENERATOR
C LK_VC C1
1
5
17
24
29
27
XOUT
28
XIN
30
PR117 33_04 REF_0/CPU_SEL
20 CLK_BUF _REF14
31
CLK_SDATA
CLK_SCLK 32
2
8
9
12
21
26
33
SMBus
Q38
MTN7002ZHS3
D S CLK_SCLK
10,11,20 SMB_CLK
PR 121 2.2K_04
3.3VS
PR 120 2.2K_04
D S CLK_SDATA
10,11,20 SMB_DATA
Q36
MTN7002ZHS3
CPU_SEL_During CK_PEWGD Latch Pinl
3.3VS
PR118 * 4.7k_04 REF_0/C PU_SEL
PR119 10K_04
CLK_VCC 2
U29
15
VDD _DOT VDD _SRC _I/O
18
VDD _27 VDD _CPU _I/O
VDD _SRC
VDD _CPU
3
C LK_BUF_DOT96_P 20
VDD _REF DOT_96
4
C LK_BUF_DOT96_N 20
DOT_96#
6
27M
7
27M_SS
XTAL_OU T
XTAL_IN 10
C LK_SATA 20
SR C_1/SATA 11
C LK_SATA# 20
SR C_1#/ SATA# 13
SRC_2 C LK_PCIE_ICH 20
14
REF_0/C PU_SEL SRC_2# C LK_PCIE_ICH # 20
SDA
16 CPU_STOP#
PR 122 2.2K_04
3.3VS
SCL C PU _STOP#
20
VSS_D OT CPU_1
19
VSS_27 C PU_1#
23
C LK_BUF_BCLK_P 20
VSS_SATA CPU_0
22
C LK_BUF_BCLK_N 20
VSS_SRC C PU_0#
VSS_C PU
25 CLK_PWRGD
VSS_R EF C KPWRGD/ PD #
GN D
3.3VS
SLG8SP585
9LRS3197
R328
10K_04
Q37 R322
G
43 C LKEN#
MTN 7002ZHS3 1M_04
X4 FSX5L_14.31818MHz
XI N 2 1 XOU T
3.3VS
C435 C436
33p_50V_N PO_04 33p_50V_NPO_04
PIN_30 CPU_0 CPU_1
0(default) 133MHz 133MHz
1(0.7V-1.5V) 100MHz 100MHz
CLKGEN POWER
C LK_VC C1
L33 *HCB1608KF-121T25_32mil_short
C482 C475 C 483
0.1u_16V_Y 5V_04 1u_16V_X5R_06
0.1u_16V_Y 5V_04
0.1uF near the every power pin
1.1VS_VTT
C LK_VC C2
L31
C491 C467 * HC B1608KF -121T25_32m il_short
VDD_I/O can be
0.1u_16V_Y 5V_04
ranging from
1u_16V_X5R_06
1.05V to 3.3V
0.1uF near the every power pin
EMI
REF_0/C PU _SEL
C437 *10P_50V_04
EMI Capactior
3.3VS 10,11,12,13,19,20,21,22,23,24,25,26,28,29,30,32,33,35,36, 37,42,43, 46
1.1VS_VTT 4, 6,7,19, 20,21,24,25,26, 39,41,42,43
Schematic Diagrams
3. 3VS
Sheet 2 of 53
Clock Generator
Clock Generator B - 3