Schematic Diagrams
Sequence
VCCRTC
RTCRST#
DD_ON#
5V
3V
SUS_PWR_DN_ACK
RSMRST#
ACPRESENT
PWRBTN#
Sheet 53 of 53
SLP_S4#
Sequence
1.5V
DDR1.5V_PWRGD
SLP_S3#
5VS
3.3VS
1.1VS
1.8VS
1.1VS_VTT
H_VTTPWRGD(ALL_SYS_PWRGD)
VCORE_ON
VCORE
CLKEN#
CLKIN_BCLK
SYS_PWRGD/SB_PWROK/PM_MPWROK
VDDPWRGOOD_R
BCLK_CPU_N/P
H_CPUPWRGD
SUS_STATE#
PLT_RST#
B - 54 Sequence
B 4 1 0 0
D 0 1
36mS
SPEC
MIN
9mS
1.675mS
1.276mS
240mS
SPEC
MAX
SPEC
MIN
5mS
SPEC
30mS
98.5mS
SPEC
(VDDQ)
VCORE
->H_CPUPWRGD
SPEC
0.05mS
P O W E R
S E Q U E N C E
734mS
200mS
10mS
MAX
200mS
450mS
MIN
100mS
2.17mS
1.85mS
50uS
SPEC
MIN
30uS
1.73mS
790uS
1.8mS
1.882mS
5.7mS
350uS
SPEC
0.0001mS
~
512mS
SPEC
953uS
SYS_PWRGD
->H_CPUPWRGD
~
650mS
SPEC100mS
<146.87mS
H_CPUPWRGD
-->
PLT_RST#
SPEC
MIN
1mS
500mS
MIN
99mS
?mS
SPEC
MAX
3mS
1.056mS
SPEC
MIN
1mS
5.64mS
SPEC
MIN
1mS
134.5mS
SPEC
MIN
1mS
145.876mS
1.1mS
50uS
SPEC
0.03mS
150uS
SPEC
MIN
~
2mS
60uS
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