Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Datasheet page 73

Land Listing and Signal Descriptions
Table 26. Signal Description (Sheet 8 of 10)
Name
SLP#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI[12,10:0]
Datasheet
Type
SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant
state, causes the processor to enter the Sleep state. In the Sleep
state, the processor stops providing internal clock signals to all
units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The
processor will recognize only assertion of the RESET# signal, de-
assertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is de-asserted, the processor exits Sleep state and
Input returns to Extended Stop Grant or Stop Grant state, restarting its
internal clock signals to the bus and processor core units. If
DPSLP# is asserted while in the Sleep state, the processor will exit
the Sleep state and transition to the Deep Sleep state. Use of the
SLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Sleep State enabled,
refer to the Specification Update for specific processor and
stepping guidance.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
Input
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
Input The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-
asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the
bus clock; STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
Input
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI
Input
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
Output TDO provides the serial output needed for JTAG specification
support.
The TESTHI[12,10:0] lands must be connected to the processor's
appropriate power source (refer to VTT_OUT_LEFT and
Input
VTT_OUT_RIGHT signal description) through a resistor for proper
processor operation. See
Description
Section 2.4 for more details.
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