Fsb Differential Clock Specifications (1333 Mhz Fsb); Fsb Differential Clock Specifications (1066 Mhz Fsb) - Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Datasheet

Electrical Specifications
4. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
5. Measurement taken from differential waveform.
Table 19.

FSB Differential Clock Specifications (1333 MHz FSB)

BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew
Rate
Slew Rate Matching
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). The Min period
specification is based on -300 PPM deviation from a 3 ns period. The Max period
specification is based on the summation of +300 PPM deviation from a 3 ns period and a
+0.5% maximum variance due to spread spectrum clocking.
3. In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4. Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6. Duty Cycle (High time/Period) must be between 40 and 60%
Table 20.

FSB Differential Clock Specifications (1066 MHz FSB)

BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 266 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). The Min period
specification is based on -300 PPM deviation from a 3.75 ns period. The Max period
specification is based on the summation of +300 PPM deviation from a 3.75 ns period and
a +0.5% maximum variance due to spread spectrum clocking.
3. In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4. Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Datasheet
T# Parameter
T# Parameter
Min Nom Max
331.633 — 333.367
2.99970 — 3.01538
— — 150
2.5 — 8
N/A N/A 20
Min Nom Max
265.307 — 266.693
3.74963 — 3.76922
— — 150
2.5 — 8
N/A N/A 20
1
Unit Figure Notes
MHz - 6
ns 4 2
ps 4 3
V/ns 5 4
% 5
1
Unit Figure Notes
MHz - 6
4
ns 2
4
ps 3
V/ns 5 4
% - 5
33