Table Of Contents - Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Datasheet

Contents
1 Introduction .............................................................................................................. 9
1.1 Terminology ..................................................................................................... 10
1.1.1 Processor Terminology Definitions ............................................................ 10
1.2 References ....................................................................................................... 12
2 Electrical Specifications ........................................................................................... 13
2.1 Power and Ground Lands.................................................................................... 13
2.2 Decoupling Guidelines ........................................................................................ 13
2.2.1 VCC Decoupling ..................................................................................... 13
2.2.2 VTT Decoupling ...................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
2.3 Voltage Identification ......................................................................................... 14
2.4 Reserved, Unused, and TESTHI Signals ................................................................ 16
2.5 Power Segment Identifier (PSID)......................................................................... 16
2.6 Voltage and Current Specification ........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification ........................................................ 18
2.6.3 VCC Overshoot ...................................................................................... 23
2.6.4 Die Voltage Validation ............................................................................. 24
2.7 Signaling Specifications...................................................................................... 24
2.7.1 FSB Signal Groups.................................................................................. 25
2.7.2 CMOS and Open Drain Signals ................................................................. 26
2.7.3 Processor DC Specifications ..................................................................... 27
2.7.3.1
2.7.3.2
2.8 Clock Specifications ........................................................................................... 31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 32
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 32
2.8.4 BCLK[1:0] Specifications ......................................................................... 32
3 Package Mechanical Specifications .......................................................................... 35
3.1 Package Mechanical Drawing............................................................................... 35
3.2 Processor Component Keep-Out Zones ................................................................. 39
3.3 Package Loading Specifications ........................................................................... 39
3.4 Package Handling Guidelines............................................................................... 39
3.5 Package Insertion Specifications.......................................................................... 40
3.6 Processor Mass Specification ............................................................................... 40
3.7 Processor Materials............................................................................................ 40
3.8 Processor Markings............................................................................................ 40
3.9 Processor Land Coordinates ................................................................................ 41
4 Land Listing and Signal Descriptions ....................................................................... 43
4.1 Processor Land Assignments ............................................................................... 43
4.2 Alphabetical Signals Reference ............................................................................ 66
5 Thermal Specifications and Design Considerations .................................................. 77
5.1 Processor Thermal Specifications ......................................................................... 77
5.1.1 Thermal Specifications ............................................................................ 77
5.1.2 Thermal Metrology ................................................................................. 81
5.2 Processor Thermal Features ................................................................................ 81
5.2.1 Thermal Monitor..................................................................................... 81
5.2.2 Thermal Monitor 2 .................................................................................. 82
5.2.3 On-Demand Mode .................................................................................. 83
5.2.4 PROCHOT# Signal .................................................................................. 84
5.2.5 THERMTRIP# Signal ............................................................................... 84
5.3 Platform Environment Control Interface (PECI) ...................................................... 85
5.3.1 Introduction .......................................................................................... 85
5.3.1.1
5.3.2 PECI Specifications ................................................................................. 86
5.3.2.1
Datasheet
Platform Environment Control Interface (PECI) DC Specifications..... 29
GTL+ Front Side Bus Specifications ............................................. 30
TCONTROL and TCC activation on PECI-Based Systems.................. 85
PECI Device Address ................................................................. 86
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