NEX ROBOTICS Fire Bird V ATMEGA2560 Software Manual page 79

NEX Robotics
Table 5.3: Waveform generation mode bit description
5.2.4 TIMSKn – Timer/Counter n Interrupt Mask Register
Bit 7
-
Read / Write R
Initial Value 0
Bit 5 – ICIEn: Timer/Counter n, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See "Interrupts" on page 105 in the ATMEGA2560 datasheet.) is executed when the
ICFn Flag, located in TIFRn, is set.
Bit 3 – OCIEnC: Timer/Counter n, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (See "Interrupts" on page 105 in the ATMEGA2560 datasheet.) is executed
when the OCFnC Flag, located in TIFRn, is set.
Bit 2 – OCIEnB: Timer/Counter n, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter n Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See "Interrupts" on page 105 in the ATMEGA2560 datasheet.) is executed
when the OCFnB Flag, located in TIFRn, is set.
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6 5 4
- ICIEn
R R/W R
0 0 0
Fire Bird V Software Manual
3 2
- OCIEnC OCIEnB
R/W R/W
0 0
1 0
OCIEnA TOIEn
R/W R/W
0 0
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