7.2.5 ADCL and ADCH – The ADC Data Register
Case 1: ADLAR = 0;
Initial value
0
Read / Write
R
Bit
15
ADCH
ADCL
ADC7
Bit
7
Read / Write
R
Initial value
0
Case 2: ADLAR = 1; (Left adjust)
Initial value
0
Read / Write
R
Bit
15
ADCH
ADC9
ADCL
ADC1
Bit
7
Read / Write
R
Initial value
0
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two's complement form. When ADCL is read, the
ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted
and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is
sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in
ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right
adjusted.
7.3 Functions for ADC
7.3.1 Function to configure pins for ADC (called inside the "port_init()" function)
//ADC pin configuration
void
adc_pin_config (void)
{
DDRF = 0x00;
//set PORTF direction as input
PORTF = 0x00;
//set PORTF pins floating
DDRK = 0x00;
//set PORTK direction as input
PORTK = 0x00;
//set PORTK pins floating
}
© NEX Robotics Pvt. Ltd. and ERTS Lab IIT Bombay, INDIA
ACIS1
ACIS0
Interrupt mode
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge
1
1
Comparator Interrupt on Rising Output Edge
Table 7.4: ACIS1/ACIS0 settings
0
0
R
R
14
13
ADC6
ADC5
6
5
R
R
0
0
0
0
R
R
14
13
ADC8
ADC7
ADC0
6
5
R
R
0
0
Fire Bird V ATMEGA2560 Software Manual
0
0
R
R
12
11
ADC4
ADC3
ADC2
4
3
R
R
0
0
0
0
R
R
12
11
ADC6
ADC5
ADC4
4
3
R
R
0
0
0
0
0
R
R
R
10
9
8
ADC9
ADC8
ADC1
ADC0
2
1
0
R
R
R
0
0
0
0
0
0
R
R
R
10
9
8
ADC3
ADC2
2
1
0
R
R
R
0
0
0
100
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