Serial Communication - NEX ROBOTICS Fire Bird V ATMEGA2560 Software Manual

8. Serial Communication

Serial Communication using UART
The Fire Bird V can communicate with other robots / devices serially using either wired link or
wireless module. Serial communication is done in asynchronous mode. In the asynchronous
mode, the common clock signal is not required at both the transmitter and receiver for data
synchronization.
ATMEGA2560 have four USART (0 to 3) ports available for serial communication.
1. RS232 Serial Communication on UART1.
2. USB Communication using FT232 USB to serial converter on UART2.
3. ZigBee Wireless Communication on UART0 (if XBee wireless module is installed).
4. TTL level serial communication pins on the expansion port on the microcontroller
adaptor board by UART3.
8.1 Registers involved in the serial communication
Note: in the following registers 'n' represents the UART number which can be 0, 1, 2 or 3.
8.1.1 UCSRnA – USART Control and Status Register A
Bit 7
RXCn
Read / Write R
Initial Value 0
Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit in the section
8.1.2).
Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is
automatically cleared when a transmit complete interrupt is executed, or it can be cleared by
writing a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit in the section 8.1.2 in the ATMEGA2560 datasheet).
Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
© NEX Robotics Pvt. Ltd. and ERTS Lab IIT Bombay, INDIA
6 5
TXCn UDREn
R/W R
0 0
Fire Bird V ATMEGA2560 Software Manual
4 3
FEn DORn UPEn
R R
0 0
2 1 0
U2Xn MPCMn
R R/W R/W
0 0 0
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