NEX ROBOTICS Fire Bird V ATMEGA2560 Software Manual page 66

NEX Robotics
Note:
• n = 7, 6, 5 or 4.
• When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the
bits are changed.
• Compare table 4.1 and 4.2. Interrupt 0 to 3 and Interrupt 4 to 7 are bit different in nature.
4.1.1.3 EIMSK – External Interrupt Mask Register
Bit 7
INT7
Read / Write R/W
Initial Value 0
Bits 7:0 – INT7:0: External Interrupt Request 7 - 0 Enable
When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one),
the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Registers – EICRA and EICRB – defines whether the external
interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins
will trigger an interrupt request even if the pin is enabled as an output. This provides a way
of generating a software interrupt.
4.1.1.4 EIFR – External Interrupt Flag Register
Bit 7
INT7
Read / Write R/W
Initial Value 0
Bits 7:0 – INTF7:0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in
EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note
that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these
pins will be disabled. This may cause a logic change in internal signals which will set the
INTF3:0 flags. See "Digital Input Enable and Sleep Modes" on page 74 of the
ATMEGA2560 datasheet for more information.
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6 5
INT6 INT5 INT4
R/W R/W
0 0
6 5
INT6 INT5 INT4
R/W R/W
0 0
Fire Bird V Software Manual
4 3
INT3 INT2
R/W R/W R/W
0 0
4 3
INT3 INT2
R/W R/W R/W
0 0
2 1 0
INT1 INT0
R/W R/W
0 0 0
2 1 0
INT1 INT0
R/W R/W
0 0 0
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