NEX ROBOTICS Fire Bird V ATMEGA2560 Software Manual page 104

Bit 4 – FEn: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received. I.E.
when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing to UCSRnA.
Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
bit to zero when writing to UCSRnA.
Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider
from 16 to 8 effectively doubling the transfer rate for asynchronous communication.
Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address
information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more
detailed information see "Multi-processor Communication Mode" on page 222 of the
ATMEGA2560 datasheet.
8.1.2 UCSRnB – USART Control and Status Register n B
Bit 7
RXCIEn
Read / Write R/W
Initial Value 0
Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
© NEX Robotics Pvt. Ltd. and ERTS Lab IIT Bombay, INDIA
6 5
TXCIEn UDRIEn
R/W R/W
0 0
Fire Bird V ATMEGA2560 Software Manual
4 3
RXENn TXENn UCSZn2
R/W R/W
0 0
2 1
RXB8n TXB8n
R/W R R/W
0 0
0
0
104