Omron SYSMAC CJ - REFERENCE MANUAL 08-2008 Reference Manual page 311

Timer and Counter Instructions
Operand Specifications
Description
Data
BCD
Binary
Note S through S+7 must be in the same data area.
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM addresses in
binary
Indirect DM/EM addresses in
BCD
Constants
Data Registers
Index Registers
Indirect addressing using
Index Registers
When the execution condition for MTIM(543)/MTIMX(554) is ON and the reset
and timer bits are both OFF, MTIM(543)/MTIMX(554) increments the PV in
D2. If the pause bit is turned ON, the timer will stop incrementing the PV, but
the PV will retain its value. MTIM(543)/MTIMX(554) will resume timing when
the pause bit goes OFF again.
Corresponding bit
(Completion Flag) in D1
Range
One word for each of 8 timer SV:
#0000 to #9999
One word for each of 8 timer SV:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
D1
CIO 0000 to CIO 6143
W000 to W511
H000 to H511
A448 to A959
T0000 to T4095
C0000 to C4095
D00000 to D32767
E00000 to E32767
En_00000 to En_32767
(n = 0 to C)
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
---
---
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Section 3-6
D2 S
CIO 0000 to
CIO 6136
W000 to W504
H000 to H504
A000 to A952
T0000 to T4088
C0000 to C4088
D00000 to
D32760
E00000 to
E32760
En_00000 to
En_32760
(n = 0 to C)
DR0 to DR15 ---
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