Multi-Interlock Differentiation Hold; Multi-Interlock Differentiation Release, And - Omron SYSMAC CJ - REFERENCE MANUAL 08-2008 Reference Manual

Sequence Control Instructions
3-5-5 MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-INTERLOCK
DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR:
MILH(517), MILR(518), and MILC(519)
Purpose
Ladder Symbols
Operands
Operand Specifications
214
Interlocks all outputs between MILH(517) (or MILR(518)) and MILC(519)
when the execution condition for MILH(517) (or MILR(518)) is OFF. MILH(517)
(or MILR(518)) and MILC(519) are normally used in pairs.
Unlike the IL(002)/ILC(003) interlocks, the MILH(517)/MILC(519) and
MILR(518)/MILC(519) interlocks can be nested. The operation of differenti-
ated instructions is different for interlocks created with MILH(517) and
MILR(518).
These instructions are supported only by CS/CJ-series CPU Unit Ver. 2.0 or
later.
MILH(517)
N: Interlock Number
N
D: Interlock Status Bit
D
MILR(518)
N
N: Interlock Number
D D: Interlock Status Bit
MILC(519)
N N: Interlock Number
N: Interlock Number
The interlock number must be between 0 and 15. Match the interlock number
of the MILH(517) (or MILR(518)) instruction with the same number in the cor-
responding MILC(519) instruction.
The interlock numbers can be used in any order.
D: Interlock Status Bit
• ON when the program section is not interlocked.
• OFF when the program section is interlocked.
When the interlock is engaged, the Interlock Status Bit can be force-set to
release the interlock. Conversely, when the interlock is not engaged, the Inter-
lock Status Bit can be force-reset to engage the interlock.
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
EM Area without bank
EM Area with bank
Indirect DM/EM
addresses in binary
N
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Section 3-5
D
CIO 000000 to CIO 614315
W00000 to W51115
H00000 to H51115
A00000 to A95915
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