ZiLOG Z80-CPU Technical Manual page 76

A.C. Characteristics
Z80-CPU
T A
=
oOe
to 70
o
e,
Vee
=
+5V ± 5%, Unless Otherwise Noted.
Signal Symbol Parameter
Min
tc
Clock Periuc.l
.4
<I>
tw«I>H) Clock Pulse Width. Clock High 180
twt<l>l)
Clock Pulse Width. Clock Low
180
II",
r
Clock Rise :.II1d F<.I1l Time
tD(AD)
Address Output Delay
tF(AD)
Delay to Float
A O _ 15
t: u : m
Address Stable Prior to MREO (Memury Cycle) III
laei
Address Stable Prior to 10RO. RD or WR (I/O Cycle) 121
lea
Address Stable from
RIJ,
WR, IORQ or MREQ 131
leaf
Address Stable From RD or WR During Flout 141
• tD(D)
Data Output Delay
tF(D)
De,"y to Float During Write Cycle
tS<I>(D)
Data Setup Time to Rising Edge of Clock During M I Cycle 50
DO_7 ts1i" (0)
Data Setup Time to Falling Edge or Clut.:k During M2 to M5 60
Idem
Data Stable Prior to WR (Memory Cycle)
15
tdci
Data Stable Prior to WR (I/O Cycle)
161
tcdf
Data Stable From WR
171
tH
Any Hold Time for Setup Time
0
tDl1i" (MR)
MREO Delay From Falling Edge of Clock, MREO low
IDH<I> (MR)
MREO Delay From Rising Edge of Clock, MREO High
MREO
tDH1i"(MR)
MREO Delay From Falling Edge of Clock. MRE'jHigh
Iw (MRl)
Pulse Width. MREO low 181
Iw(MRH)
Pulse Width, MREO High
. 191
tDl<l> (IR)
10RO Delay From Rising Edge of Clock, 10RO low
IORO
tDL1i" (IR)
10RO Delay From Falling Edge of Clock, IORO low
tDH<I> (IR)
10RO Delay From Rising Edge of Clock, 10RO High
tDH1i"(IR)
IORO Delay From Falling Edge of Clock, 10RO High
tDl<l> (RD)
RD Delay From Rising Edge of Clock, RD low
Ri5
tDl1i" (RD)
RD Delay From Falling Edge of Clock, RD low
tDH<I> (RD)
RD Delay From Rising Edge of Clock, RD High
tDH<i>(RD)
RD Delay From Falling Edge of Clock, RD High
IDl<l> (WR)
WR Delay From Rising Edge of Clock, WR low
WR
tDl1i"(WR)
WR Delay From Falling Edge of Clock, WR Low
tDH<I>(WR)
WR Delay From Falling Edge of Clock, WR High
tw (WRl)
Pulse Width, WR low [101
MI
tDl(MI)
M I Delay From Rising Edge of Clock,
Mi
low
tDH
(Mil
MT
Delay From Rising Edge of Clock, M I High
RFSH
tDl(RF)
RFSH Delay From Rising Edge of Clock, RFSH low
IDH (RF)
RFSH Delay From Rising Edge of Clock, RFSH High
WAIT
Is (WT)
WAIT Setup Time to Falling Edge of Clock 70
HALT
tD(HT)
HALT Delay Time Fro", Falling Edge of Clock
INT
ts (IT)
INT Selup Time
10
Rising Edge of Clock
>
80
NMI
tw(NMl)
Pulse Width, NM I low
80
BUSRO
ts (BO)
BUSRO Selup Time
10
Rising Edge of Clock 80
BUSAK
IDl(BA)
BUSAK Delay From Rising Edge of Clock, BUSAK low
IDH (BA)
BUSAK Delay From Falling Edge of Clock, BUSAK High
RESET
Is (RS)
RESET Setup Time to Rising Edge of Clock 90
IF (C)
Delay to Float (MREO, 10RO, RD and WR)
tmr
Mi
Slable Prior to 10RO (lnterrupl Ack.) IIII
NOTES:
A.
Data should be enabled onto the
CPU
data bus when RD is active. During interrupt acknowledge data
should be enabled when
MI
and
fORQ
arc both active.
B. All
control signals are internally synchronized. so they may be totally asynchronous with respect
10
the clock.
C. The RESET signal must be active for a minimum of 3 dock cycles.
D. Output Delay vs. Loaded Capacitance
TA
=
70°(,
Vcc::: +5V
±5'/r .
Max Unit
1121
fJsec
[EJ
nsec
2000 osec
30 osee
145
osee
110 osee
osee
osee
nsec
nsee
230 osec
90 nsec
osec
nsee
nsec
nsee
osee
100 osee
100 nsec
100 osee
osee
osee
90 osee
110 osee
100 osee
110 osec
100 osec
130 osee
100 osee
110 osee
80 osec
90 osee
100 osee
osee
130 osee
130 osee
180
osee
150 osee
nsec
300 nsec
nsec
nsec
nsec
120 nsec
110 nsec
nsec
100
nsec
nsec
Add 10nsee delay for each SOpf increase in load up to a maximum of 200pf for the data bus & 1 OOpf for
address
&
control lines
E. Although static by design. testing guarantees tw(,pH) of 200 I1sec maximum
70
Test Condition
C l = 50pF
[IJ
tacm = tw(<I>H)
+
If-75
[2J
taei = tc -80
[3J
Ica = tw(<I>l)
+
tr - 40
[4J
tcaf= IW(<I>l)
+
tr - 60
C L
=
SOpF
[5J
tdem
=
te - 210
[6J
tdci
=
tw(cJ>L)
+
tr - 210
[7J
tedf
=
tw(cJ>L)
+
tr -80
C l =50pF
[8J tw (MRl) = tc - 40
[9J tw(MRH) = tw(<I>H)
+
tf- 30
C l =50pF
C l = 50pF
C L = 50pF
C L
=
SOpF
C L
=
SOpF
C L = 50pF
C l ~ 50pF
TEST POINT
load circuit for Output