ZiLOG Z80-CPU Technical Manual page 37

SOURCE
'ADD'
IX DD DD
09 19
IV FD
FD
09
19
DESTINATION
ADD WITH CARRV AND HL ED
ED
SET FLAGS 'A DC'
4A 5A
SUB WITH CARRV AND
HL ED ED
SET FLAGS 'SBC'
42
52
INCREMENT
'INC'
DECREMENT 'DEC'
16 BIT ARITHMETIC
TABLE 5.3-8
ROTATE AND SHIFT
DD
39
FD
39
ED
ED
6A 7A
ED ED
62 72
IX IV
DO
29
DD
23
DO
2B
FD
29
FD
23
FD
2B
A major capability of the Z-80 is its ability to rotate or shift data in the accumulator, any general pur-
pose register, or any memory location. All of the rotate and shift OP codes are shown in table 5.3-9. Also
included in the Z-80 are arithmetic and logical shift operations. These operations are useful in an extremely
wide range of applications including integer multiplication and division. Two BCD digit rotate instructions
(RRD and RLD) allow a digit in the accumulator to be rotated with the two digits in a memory location
pointed to by register pair HL. (See figure 5.3-9). These instructions allow for efficient BCD arithmetic.
BIT MANIPULATION
The ability to set, reset and test individual bits in a register or memory location is needed in almost
every program. These bits may be flags in a general purpose software routine, indications of external con-
trol conditions or data packed into memory locations to make memory utilization more efficient.
The Z-80 has the ability to set, reset or test any bit in the accumulator, any general purpose register
or any memory location with a single instruction. Table 5.3-10 lists the 240 instructions that are available
for this purpose. Register addressing can specify the· accumulator or any general purpose register on which
the operation is to be performed. Register indirect and indexed addressing are available to operate on
external memory locations. Bit test operations set the zero flag (Z) if the tested bit is a zero. (Refer to
section 6.0 for further explanation of flag operation).
JUMP, CALL AND RETURN
Figure 5.3-11 Iists all of the jump, call and return instructions implemented in the Z-80CPU. Ajump
is a branch in a program where the program counter is loaded with the 16-bit value as specified by one of the
three available addressing modes (Immediate Extended, Relative or Register Indirect). Notice that the jump
group has several different conditions that can be specified to be met before the jump will be made. If
these conditions are not met, the program merely continues with the next sequential instruction. The
conditions are all dependent on the data in the flag register. (Refer to section 6.0 for details on the flag
register). The immediate extended addressing is used to jump to any location in the memory. This in-
struction requires three bytes (two to specify the 16-bit address) with the low order address byte first
followed by the high order address byte.
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