ZiLOG Z80-CPU Technical Manual page 38

TYPE
OF
ROTATE
OR
SHIFT
Source and Destination
A B C
0
E
H
'RLC'
CB
CB CB. CB CB CB
07 00 01 02 03 04
'RRC'
CB
CB CB
CB
CB CB
OF DB 09 OA DB DC
'RL' CB CB
CB CB CB CB
17
10 11 12 13 14
'RR'
CB
CB CB CB CB CB
1F 18 19 lA
lB
lC
'SLA'
CB CB CB CB CB
CB
27 20 21 22 23 24
'SRA' CB CB CB CB CB CB
2F 2B
29 2A 2B 2C
'SRL'
CB CB
CB
CB
CB
CB
3F 38 39 3A 3B 3C
r
'RLD'
'RRD'
L
CB
05
CB
OD
CB
15
CB
1D
CB
25
CB
2D
CB
3D
!HL) !IX +d) (lY+d)
CB
DO
Fo
CB CB
06 d
d
06
06
CB
DO FD
CB CB
DE
d d
DE DE
oD
Fe
CB
CB CB
16
d d
16
16
CB
DD
Fe
CB CB
IE
d d
IE IE
CB
DD FD
CB CB
26 d
d
26 26
CB
DD
Fo
CB
CB
2E d
d
2E
2E
CB
DD Fe
CB CB
3E
d
d
3E 3E
ED
6F
ED
67
ROTATES AND SHIFTS
TABLE 5.3-9
Rotate
Left Circular
~
1.----,:1
Ro""
~ ~
Right Circular
~ ~
Rotate
Left
Rotate
Right
~ r C - ~
Shift
~ ~ ~
Right Arithmetic
~
r.J __
~
Shift
~
I '
r
Right Logical
o
H
1 (HL)
:~~;e
Digit
~-A~C~cT'~~
_ _
~==~~~
For example an unconditional Jump to memory location 3E32H would be:
Address A
I
C3
I
OP Code
A+ 1
~
Low order address
A+2
~
High order address
The relative jump instruction uses only two bytes, the second byte is a signed two's complement dis-
placement from the existing PC. This displacement can be in the range of
+
129 to -126 and is measured
from the address of the instruction OP code.
Tmee types of register indirect jumps are also included. These instructions are implemented by loading
the register pair HL or one of the index registers IX or IY directly into the PC. This capability allows for
program jumps to be a function of previous calculations.
A call is a special form of a jump where the address of the byte following the call instruction is
pushed onto the stack before the jump is made. A return instruction is the reverse of a call because the
data on the top of the stack is popped directly into the PC to form a jump address. The call and return
instructions allow for simple subroutine and interrupt handling, Two special return instructions have been
included in the Z-80 family of components. The return from interrupt instruction (RETI) and the return
from non maskable interrupt (RETN) are treated in the CPU as an unconditional return identical to the OP
code C9H. The difference is that (RETI) can be used at the end of an interrupt routine and all Z-80 peripheral
chips will recognize the execution of this instruction for proper control of nested priority interrupt handling.
This instruction coupled with the Z-80 peripheral devices implementation simplifies the normal return from
nested interrupt. Without this feature the following software sequence would be necessary to inform the
interrupting device that the interrupt routine is completed:
32