ZiLOG Z80-CPU Technical Manual page 15

RESET
BUSRQ
(Bus Request)
BUSAK
(Bus Acknowledge)
Input, active low. RESET forces the program counter to zero and initializes
the CPU. The CPU initialization includes:
1) Disable the interrupt enable flip-flop
2) Set Register I = OOH
3) Set Register R
=
OOH
4) Set Interrupt Mode 0
During reset time, the address bus and data bus go to a high impedance state
and all control output signals go to the inactive state.
Input, active low. The bus request signal is used to request the CPU address
bus, data bus and tri-state output control signals to go to a high impedance
state so that other devices can control these buses. When BUSRQ is activated,
the CPU will set these buses to a high impedance state as soon as the current
CPU machine cycle is terminated.
Output, active low. Bus acknowledge is used to indicate to the requesting
device that the CPU address bus, data bus and tri-state control bus signals
have been set to their high impedance state and the external device can now
control these signals.
Single phase TTL level clock which requires only a 330 ohm pull-up resistor
to +5 volts to meet all clock requirements ..
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