ZiLOG Z80-CPU Technical Manual page 67

WAIT
+5V
1
I~
M1
-I
I
T,
I
T2
I
Tw
I
T3
I
T4
I
M1
S
S
0
0 0
of--
<I>
<1>.
7474 7474
C
Q
r - -
C
Q
M1
\ I
R
R
r
I
WAIT
L.J
+5V
+5V
FIGURE 9.0-3
ADDING ONE WAIT STATE TO AN M1 CYCLE
+5V
~
MREO
S
<I>
0 0 0
7474 7474
MREO\
<I>
a
IT
C
C
R R
WAIT
L-J
+5V +5V
FIGURE 9.0-4
ADDING ONE WAIT STATE TO ANY MEMORY CYCLE
INTERFACING DYNAMIC MEMORIES
This section is intended only to serve as a brief introduction to interfacing dynamic memories. Each
individual dynamic RAM has varying specifications that will require minor modifications to the description
given here and no attempt will be made in this document to give details for any particular RAM. Separate
application notes showing how the Z80-CPU can be interfaced to most popular dynamic RAM's are
available from Zilog.
Figure 9.0-5 illustrates the logic necessary to interface 8K bytes of dynamic RAM using 18 pin 4K
dynamic memories. This figure assumes 'that the RAM's are the only memory in the system so that A12 is
used to select between the two pages of memory. During refresh time, all memories in the system mustbe
read. The CPU provides the proper refresh address on lines AD through A 6 . To add additional memory to
the system it is necessary to only replace the two gates that operate on Al2 with a decoder that operates
on all required address bits. For larger systems, buffering for the address and data bus is also generally
required.
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