Z80-Cpu Pin Description - ZiLOG Z80-CPU Technical Manual

3.0 Z-BO CPU PIN DESCRIPTION
The Z-80 CPU is packaged in an industry standard 40 pin Dual In-Line Package. The I/O pins are shown
in figure 3.0-1 and the function
0
f each is described below.
SYSTEM
CONTROL
CPU
M,
MREQ
10RQ
RD
WR
CONTROL INT
NMI
RESET
CPU {BUSRQ
BUS
CONTROL BUSAK
AO-A15
(Address Bus)
Ml
(Machine Cycle one)
MREQ
(Memory Request)
'I'
+5V
GND
27
19
20
21
22
28
18
24
16
17
26
25
23
6
11
29
Z-80 CPU
Z-BO PIN CONFIGURATION
FIGURE 3.0-1
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
14
15
12
8
7
9
10
13
ADDRESS
BUS
DATA
BUS
Tri-state output, active high. AO-A15 constitute a 16-bit address bus. The
address bus provides the address for memory (up to 64K bytes) data
exchanges and for I/O device data exchanges. I/O addressing uses the 8 lower
address bits to allow the user to directly select up to 256 input or 256 output
ports. AO is the least significant address bit. During refresh time, the lower
7 bits contain a valid refresh address.
Tri-state input/output, active high. DO-D7 constitute an 8-bit bidirectiQnai
data bus. The data bus is used for data exchanges with memory and I/O
devices.
Output, active low. M 1 indicates that the current machine cycle is the OP
code fetch cycle of an instruction execution. Note that during execution
of 2-byte op-codes, Ml is generated as each op code byte is fetched. These
two byte op-codes always begin with CBH, DDH, EDH or FDH. Ml also
occurs with 10RQ to indicate an interrupt acknowledge cycle.
Tri-state output, active low. The memory request signal indicates that the
address bus holds a valid address for a memory read or memory write
operation.
7