ZiLOG Z80-CPU Technical Manual page 24

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NON MASKABLE INTERRUPT RESPONSE
Figure 4.0-6 illustrates the request/acknowledge cycle for the non maskable interrupt. This signal is
sampled at the same time as the interrupt line, but this line has priority over the normal interrupt and it can
not be disabled under software control. Its usual function is to provide immediate response to important
signals such as an impending power failure. The CPU response to a non maskable interrupt is similar to a
normal memory read operation. The only difference being that the content of the data bus is ignored while
the processor automa tically stores the PC in the external stack and jumps to location 0066 H . The service
routine for the non maskable interrupt must begin at this location if this interrupt is used.
HALT EXIT
Whenever a software halt instruction is executed the CPU begins executing Nap's until an interrupt is
received (either a non maskable or a maskable interrupt while the interrupt flip flop is enabled). The two
interrupt lines are sampled with the rising clock edge during each T4 state as shown in figure 4.0-7. If a non
maskable interrupt has been received or a maskable interrupt has'been received and the interrupt enable
flip-flop is set, then the halt state will be exited on the next rising clock edge. The following cycle will then
be an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are
received at this time, then the non maskable one will be acknowledged since it has highest priority. The
purpose of executing Nap instructions while in the halt state is to keep the memory refresh signals active.
Each cycle in the halt state is a normal Ml (fetch,) cycle except that the data received from the memory is
ignored and a Nap instruction is forced internally to the CPU. The halt acknowledge signal is active during
this time to indicate that the processor is in the halt state.
Last M Cycle
MI
Last T Time T1 T2
T3
T4 T1
~ ~
~
~ ~ ~ ~
r--
-
-
---_L L----
- - - - -
------ -----
- - - - -
-----
1--
-
---
- - - -
r------
- - - - - - - - - - - - -
------
-
AO-A15
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PC
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REFRESH
1
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HALT
INTor
NMI
\ I
\
\
I
\
NON MASKABLE INTERRUPT REQUEST OPERATION
FIGURE 4.0-6
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- - M1----<~I_------- M 1 - - - - - - - - - r - - - M 1
HALT INSTRUCTION
IS RECEIVED
DURING THIS
MEMORY CYCLE
HALT EXIT
FIGURE 4.()'7
18
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