ZiLOG Z80-CPU Technical Manual page 42

R
E
G
INPUT'IN'
A
0
0
R
E
S
S
I
INPUT N
DESTINATION G
'INI' - INPUT &
Inc HL, DecB
'INIR'-INP, Inc HL,
Dec B, REPEAT IF B#O
REG;
INDIR
'IND'-INPUT &
Dec HL, DecB
'INDR'-INPUT, Dec HL,
Dec B, REPEAT IF 8#0
B
C
0
E
H
L
(HL)
SOURCE
PORT ADDR ESS
ED
40
ED
48
ED
50
ED
58
ED
60
ED
68
ED
A2
ED
B2
ED
AA
ED
BA
BLOCK INPUT
COMMANDS
/
INPUT GROUP
TABLE 5.3-13
CPU CONTROL GROUP
The final table, table 5.3-15 illustrates the six general purpose CPU control instructions. The NOP is a do-
nothing instruction. The HALT instruction suspends CPU operation until a subsequent interrupt is received,
while the DI and EI are used to lock out and enable interrupts. The three interrupt mode commands set the
CPU into any of the three available interrupt response modes as follows. If mode zero is set the interrupting
device can insert any instruction on the data bus and allow the CPU to execute it. Mode 1 is a simplified
mode where the CPU automatically executes a restart (RST) to location 0038H so that no external hardware
is required. (The old PC content is pushed onto the stack). Mode 2 is the most powerful in that it allows for
an indirect call to any location in memory. With this mode the CPU forms a 16-bit memory address where
the upper 8-bits are the content of register I and the lower 8-bits are supplied by the interrupting device.
This
address points to the first of two sequential bytes in a table where the address of the service routine is
located. The CPU automatically obtains the starting address and performs a CALL to this address.
Address of interrupt {
1-----1
service routine
36
Pointer to Interrupt table. Reg.
I is upper address,
Peripheral supplies lower address