ZiLOG Z80-CPU Technical Manual page 29

5.3 INSTRUCTION OP CODES
This section describes each of the l-80 instructions and provides tables listing the OP codes for every
instruction. In each of these tables the OP codes in shaded areas are identical to those offered in the 8080A
CPU. Also shown is the assembly language mnemonic that is used for each instruction. All instruction OP
codes are listed in hexadecimal notation. Single byte OP codes require two hex characters while double
byte OP codes require'four hex characters. The conversion from hex to binary is repeated here for
convenience.
Hex Binary Decimal Hex
Binary Decimal
0 0000 0
8 =
1000 8
0001 = 1 9 1001
9
2 0010
2 A
1010 10
3 0011
3 B
1011 11
4 0100
4 C 1100 = 12
5
= 0101
5 D 1101 13
6
0110
=
6
E 1110 = 14
7
= 0111 = 7
F 1111 15
l-80 instruction mnemonics consist of an OP code and zero, one or two operands. Instructions in
which the operand is implied have no operand. Instructions which have only one logical operand or those in
which one operand is invariant (such as the Logical OR instruction) are represented by a one operand
mnemonic. Instructions which may have two varying operands are represented by two operand mnemonics.
LOAD AND EXCHANGE
Table 5.3-1 defines the OP code for all of the 8-bit load instructions implemented in the l-80 CPU.
Also shown in this table is the type of addressing used for each instruction. The source of the data is found
on the top horizontal row while the destination is specified by the left hand column. For example, load
register C from register B uses the OP code 48H. In all of the tables the OP code is specified in hexadecimal
notation and the 48H (=01001000 binary) code is fetched by the CPU from the external memory during
M1 time, decoded and then the register transfer is automatically performed by the CPU.
The assembly language mnemonic fot this entire group is LD, followed by the destination followed
by the source (LD DEST., SOURCE). Note that several combinations of addressing modes are possible. For
example, the source may use register addressing and the destination may be register indirect; such as load
the memory location pointed to by register HL with the contents of register D. The OP code for this
operation would be 72. The mnemonic for this load instruction would be as follows:
LD (HL),D
The parentheses around the HL means that the contents of HL are used as a pointer to a memory location.
In all l-80 load instruction mnemonics the destination is always listed first, with the source following. The
l-80 assembly language has been defined for ease of programming. Every instruction is self documenting
and programs written in l-80 language are easy to maintain.
Note in table 5.3-1 that some load OP codes that are available in the l-80 use two bytes. This is an
efficient method of memory utilization since 8,16,24 or 32 bit instructions ate implemented in the l-80.
Thus often utilized instructions stich as arithmetic or logical operations are only 8-bits which results in
better memory utilization than is achieved with fixed instruction sizes such as 16-bits.
All load instructions using indexed addressing for either the source or destination location
actually use three bytes of memory with the third byte being the displacement d. For example a load
register E with the operand pointed to by IX with an offset of +8 would be written:
LD E, (IX +8)
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