ZiLOG Z80-CPU Technical Manual page 10

MAIN ~EG SET
ALTERNATE REG SET
A
A
"
,/
ACCUMULATOR FLAGS ACCUMULATOR FLAGS
A
B
0
H
F A'
C
B'
E 0'
L H'
INTERRUPT
I
MEMORY
VECTOR REFRESH
I R
INDEX REGISTER IX
INDEX REGISTER IY
STACK POINTER SP
PROGRAM COUNTER PC
I'
>
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F·'
C'
E'
L'
SPECIAL
PURPOSE
REGISTERS
Z-80 CPU REGISTER CONFIGURATION
FIGURE 2.0-2
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GENERAL
PURPOSE
REGISTERS
3. Two Index Registers (IX & IY). The two independent index registers hold a 16-bit base address that
is used in indexed addressing modes. In this mode, an index register is used as a base to point to a
region in memory from which data is to be stored or retrieved. An additional byte is included in
indexed instructions to specify a displacement from this base. This displacement is specified as a two's
complement signed integer. This mode of addressing greatly simplifies many types of programs,
especially where tables of data are used.
4. Interrupt Page Address Register (I). The Z-80 CPU can be operated in a mode where an indirect call
to any memory location can be achieved in response to an interrupt. The I Register is used for this
purpose to store the high order 8-bits of the indirect address while the interrupting device provides the
lower 8-bits of the address. This feature allows interrupt routines to be dynamically located anywhere
in memory with absolute minimal access time to the routine.
5. Memory Refresh Register (R). The Z-80 CPU contains a memory refresh counter to enable dynamic
memories to be used with the same ease as static memories. Seven bits of this 8 bit register are auto-
matically incremented after each instruction fetch. The eighth bit will remain as programmed as the
result of an LD R, A instruction. The data in the refresh counter is sent out on the lower portion of
the address bus along with a refresh control signal while the CPU is decoding and executing the fetched
instruction. This mode of refresh is totally transparent to the programmer and does not slow down the
CPU operation. The programmer can load the R register for testing purpOSes, but this register is normally
not used by the programmer. J)uring refresh, the contents of the I register are placed on the upper 8 bits of
the address bus. .
Accumulator and Flag Registers
The CPU includes two independent 8-bit accumulators and associated 8-bit flag registers. The accumu-
lator !tolds the results of 8-bit arithmetic or logical operations while the flag register indicates specific
conditions for 8 or 16-bit operations, such as indicating whether or not the result of an operation is equal
to zerO. The programmer selects the accumulator and flag pair that he wishes to work with with a single
exchange instruction so that he may easily work with either pair.
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