ZiLOG Z80-CPU Technical Manual page 66

Every computer system requires I/O circuits to allow it to interface to the "real world." In this simple
example it is assumed that the output is an 8 bit control vector and the input is an 8 bit status word. The
input data could be gated onto the data bus using any standard tri-state driver while the output data could
be latched with any type of standard TTL latch. For this example we have used a Z80-PIO for the I/O
circuit. This single circuit attaches to the data bus as shown and provides the required 16 bits of TTL
compatible I/O. (Refer to the Z80-PIO manual for details on the operation of this circuit.) Notice in this
example that with only three LSI circuits, a simple oscillator and a single 5 volt power supply, a
powerful computer has been implemented.
ADDING RAM
Most computer systems require some amount of external Read/Write memory for data storage and to
implement a "stack." Figure 9.0-2 illustrates how 256 bytes of static memory can be added to the previous
example. In this example the memory space is assumed to be organized as follows:
MREQ· RD
CE,
A 10
CE 2
JAO_A
g
\;
'K x 8
ROM
d
o
-d 7
V
lK bytes
ROM
256 bytes
RAM
Address
OOOOH
03FFH
0400H
04FFH
ADDRESS BUS
AO-A7
J
!!Q..
00
CE,
256x4
~
RAM
R/W
CE 2
j\
~
d O -d 3
~
V
DATA BUS
FIGURE 9.()'2
.M!!.Q.!!Q.
A,O
-.:..:
~
ROM & RAM IMPLEMENTATION EXAMPLE
AO-A7
\J
00
CE,
~
256 x4
RAM
AlO
R/W
CE 2 t--=-=-
/\
~
d 4 -d 7
IV
In this diagram the address space is described in hexidecimal notation. For this example, address bit AlO
separates the ROM space from the RAM space so that it can be used for the chip select function. For
larger amounts of external ROM or RAM, a simple TTL decoder will be required to form the chip selects.
MEMORY SPEED CONTROL
For many applications, it may be desirable to use slow memories to reduce costs. The WAIT line on
the CPU allows the Z-80 to operate with any speed memory. By referring back to section 4 you will notice
that the memory access time requirements are most severe during the Ml cycle instruction fetch. All other
memory accesses have an additional one half of a clock cycle to be completed. For this reason it may be
desirable in some applications to add one wait state to.the MI cycle so that slower memories can be used.
Figure 9.0-3 is an example of a simple circuit that will accomplish this task. This circuit can be changed to
add a single wait state to any memory access as shown in Figure 9.0-4.
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