ZiLOG Z80-CPU Technical Manual page 20

Figure 4.0-2A illustrates how a WAIT request signal will lengthen any memory read or write opera-
tion_ This operation is identical to that previously described for a fetch cycle. Notice in this figure that a
separate read and a separate write cycle are shown in the same figure although read and write cycles can
never occur simultaneously.
<I'
AO -A15
RD
DATA BUS
(DO- 07)
DATA BUS
(DO- 07)
WAIT
-
-
--
T1
T2
Tw
Tw
T3
T1
~
r--L......
r----t-r----t-r----t-r----t-
I MEMORY ADDR.
~
\
I
\ I
IN
\ I
DATA OUT
1------ 1-l..J..-- l.....C-
-IL.--
1 - - - - -
----
1 - - - - -
---
I--
- - 1 - - - - -
1-----
MEMORY READ OR WRITE CYCl-ES WITH WAIT STATES
FIGURE 4.0-2A
INPUT OR OUTPUT CYCLES
Ir---
--
--
}
READ
CYCLE
}
WRITE
CYCLE
Figure 4_0-3 illustrates an I/O read or I/O write operation. Notice that during I/O operations a single
wait state is automatically inserted. The reason for this is that during I/O operations, the time from when
the 10RQ signal goes active until the CPU must sample the WAIT line is very short and without this extra
state sufficient time does not exist for an I/O port to decode its address and activate the WAIT line if a wait
is required. Also, without this wait state it is difficult to design MOS I/O devices that can operate at full
CPU speed. During this wait state time the WAIT request signal is sampled. During a read I/O operation,
the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read. For
I/O write operations, the WR line is used as a clock to the I/O port, again with sufficient overlap timing
automatically provided so that the rising edge may be used as a data clock. -
Figure 4.0-3A illustrates how additional wait states may be added with the WAIT line. The operation
is identical to that previously described.
BUS REQUEST/ACKNOWLEDGE CYCLE
Figure 4.04 illustrates the timing for a Bus Request/Acknowledge cycle. The BUSRQ signal is
sampled by the CPU with the rising edge of the last clock period of any machine cycle. If the BUSRQ
signal is active, the CPU will set its address, data and tri-state control signals to the high impedance state
with the rising edge of the next clock pulse. At that time any external device can control the buses
to
transfer data between memory and I/O devices. (This is generally known as Direct Memory Access [DMA]
using cycle stealing). The maximum time for the CPU to respond to a bus request is the length of a machine
cycle and the external controller can maintain control of the bus for as many clock cycles as is desired.
Note, however, that if very long DMA cycles are used, and dynamic memories are being used, the external
controller must also perform the refresh function. This situation only occurs if very large blocks of data are
transferred under DMA control Also note that during a bus request cycle, the CPU cannot be interrupted
by either a
NMI
or an INT signal
14