Counter Input Signal Connection - Advantech PCIE-1810 User Manual

2.3.6

Counter Input Signal Connection

The voltage logic level between the counter input (counter clock, counter gate,
counter arm, and sample clock) terminals and the digital ground (DGND) terminal is
measured. To prevent undetermined or fluctuating results when input is floating, the
counter input signals are internally pulled-up. This is shown in Figure 2. 11.
For a deterministic outcome, the input voltage should either surpass the minimum
ON state value or fall below the maximum OFF state value. If the input voltage lies
between these thresholds, the result becomes indeterminate, leading to either an ON
or OFF state. Moreover, avoid supplying a voltage exceeding the maximum allowed
ON state value or going below the minimum allowed OFF state value, as it may dam-
age the device. Refer to the device specifications for the specified voltage ranges in
the ON and OFF states.
PCIE-1810 User Manual
Figure 2.11 Counter input signal connection
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